穿隧式場效電晶體由於只需低的操作電壓即可使元件運作，且擁有低的關閉漏電流和低的次臨限擺幅等優點，而成為次世代取代金氧半電晶體的一大熱門；然而傳統的矽基穿隧式場效電晶體由於矽擁有較大的能隙(約1.1 eV)，使元件特性受限於低的導通電流。III-V族材料穿隧式場效電晶體因具較低能隙寬度而有較高穿隧機率，且能保持與金氧半電晶體相近數量級的電流開關比，並同時擁有高的元件導通電流，故本論文著重於開發III-V族化合物半導體之穿隧式場效電晶體。
本論文使用了同質結構與異質結構之III-V族p-i-n摻雜材料兩種磊晶，同質結構砷化銦鎵材料之銦的成分比例為53%，鎵的比例為47%，源極為p+型砷化銦鎵；而異質結構銻砷化鎵/砷化鋁銦的能隙排列為第二型錯開能隙，由於擁有很小的有效穿隧能障，使之能產生很大的導通電流，源極為p+型砷銻化鎵。
微米尺寸穿隧式場效電晶體製程部分皆以光學曝光進行圖形定義，利用濕式蝕刻將主動區以外的區域蝕刻移除，來達成元件間的電性隔離，並探討不同沉積後熱退火方式差異。成功製作出閘極寬度為 10 μm的元件，氧化層之氧化鋁/氧化鉿EOT為2 nm，氧化層沉積後快速熱退火之元件，其77 K低溫量測下次臨限擺幅為136 mV/dec，電流開關比達2.02 × 104，汲極關閉電流為3.54 × 10-5 μA/μm。而次微米尺寸穿隧式場效電晶體部分，閘極自我對準製程已開發。

Tunnel field effect transistors (TFETs) are attractive candidates to replace MOSFETs for low power application due to the ability to make device work with a lower supply voltage, without increase in OFF state currents. However, TFETs suffer from a low ON current using large bandgap silicon based materials. For this reason, III-V material based devices with high ON current have been considered. because of the high tunneling probability due to the narrow and direct bandgap. Therefore, III-V material based TFETs are studied in this thesis.
There are two different epitaxy structures used in this study. In order to achieve the tunneling operation of n-type TFET, a heavily doped In0.53Ga0.47As is dedicated for source, n+- In0.53Ga0.47As is for drain, and undoped In0.53Ga0.47As is for channel in In0.53Ga0.47As homo-junction structure. And the type-II staggered gap heterojunction leads to high ON current, which a heavily doped GaAs0.12Sb0.88 is dedicated for source, n+- In0.95Al0.05As is for drain, and undoped In0.95Al0.05As is for channel.
In this study, a wet etching method was applied to fabricate micro scale TFETs by mesa isolation etch to the InP substrate. Different annealing processes were studied for insulators including Al2O3/HfO2 (EOT of 2 nm) by ALD. The n-TFET with best current and S.S. performance is a device with drain length of 2 μm. The characteristics of this device demonstrated the lowest S.S. of 136 mV/dec, on/off current ratio of 2.02 × 104 and minimum OFF state leakage current of 3.54 × 10-5 μA/μm in low temperature measurement(77 K). Moreover, a the sub-micro TFETs fabrication with self-aligned gate technology have been developed.

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