具四階脈波振幅調變資料相位偵測器與還原資料選擇電路之10 Gb/s時脈與資料回復電路

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研究生：	林修華 Hsiu-Hua Lin
論文名稱：	具四階脈波振幅調變資料相位偵測器與還原資料選擇電路之10 Gb/s時脈與資料回復電路 A 10 Gb/s Clock and Data Recovery with PAM-4 Data Phase Detection and Recovered Data Selection
指導教授：	鄭國興 Kuo-Hsing Cheng
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2019
畢業學年度：	107
語文別：	中文
論文頁數：	93
中文關鍵詞：	時脈與資料回復電路、四階脈波振幅調變、相位偵測器、抖動容忍度
外文關鍵詞：	Clock and data recovery, PAM-4, Phase detector, Jitter tolerance
相關次數：	點閱：11 下載：0
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隨著串列傳輸系統對資料速率的需求逐漸提升，頻寬的需求也日漸嚴苛。四階脈波振幅調變技術可以應用於串列傳輸系統，其頻寬需求僅為非歸零式訊號的一半，因此系統可以操作在較低的頻率。然而，四階脈波振幅調變資料的多個電壓準位與複雜的資料轉態情形，將會提高時脈與資料回復電路的設計難度，因此，目前文獻設計上採用多組相位偵測器或是資料轉態選擇器，以達成較高的資料轉態密度或是較小的回復時脈抖動量。
評估四階脈波振幅調變資料的特性對時脈與資料回復電路效能之影響，本論文提出一個應用於四階脈波振幅調變資料的二進位相位偵測器和還原資料選擇電路。所提出之四階脈波振幅調變資料相位偵測器，可用於偵測四階脈波振幅調變資料的各種邊緣型態，因此可增加資料轉態密度，進而獲得較佳的相位追鎖能力。論文中之設計亦使用還原資料選擇電路，以提升時脈與資料回復電路之抖動容忍度，並能降低誤碼率。避免因四階脈波振幅調變資料的急劇資料邊緣變化和多個電壓準位，造成高頻抖動容忍量下降。本論文之電路設計採用TSMC 40 nm (TN40G) 1P10M CMOS製程，操作電壓為0.9V，晶片面積為1.10 mm2，核心電路面積為0.11 mm2。輸入資料為10 Gb/s PRBS7 PAM-4時，佈局後模擬之還原時脈速率為5 GHz，還原時脈之峰對峰值20.8 pspp，方均根值3.21 psrms，功率消耗為41.6 mW。

The demand of higher data rate in serial transmission is rising, and the bandwidth requirement is more critical. 4-level pulse amplitude modulation (PAM-4) technique can be adopted to decrease bandwidth requirement to half compared to NRZ data, so the clock in the receiver also can operate at lower frequency. However, the multiple levels and complicated transitions of PAM-4 data increase the design difficulty of clock and data recovery. Therefore, current papers use multiple phase detectors or data transition selector to achieve higher transition density or less recovered clock jitter.
Considering the impact of characteristics of PAM-4 data on the performance of clock and data recovery. This thesis presents a bang-bang clock and data recovery with PAM-4 data phase detector and recovered data selection. The proposed PAM-4 bang-bang phase detector can be used on detecting all edge types of PAM-4 data. Therefore, the transition density can be increased, and then better phase tracking ability is acquired. This thesis also presents a recovered data selection circuit to enhance jitter tolerance of clock and data recovery, and is able to lower bit error rate. The circuit of this thesis is designed in 40 nm standard CMOS process with supply voltage of 0.9 V, the chip area is 1.10 mm2, the core area is 0.11 mm2. The post-layout simulation jitter of the recovered clock is 20.8 pspp and 3.21 psrm, and the total power consumption is 41.6 mW at 10 Gb/s PAM-4 27 – 1 pseudo random binary sequence (PRBS7) signal.

摘要    i
Abstract    ii
目錄    iii
圖目錄    vi
表目錄    ix
 第1章 緒論    1
1 研究動機    1
2 論文架構    4
 第2章 時脈與資料回復電路之背景簡介    5
1 時脈與資料回復電路簡介    5
1.1 相位偵測器型態    5
1.2 取樣速率    7
1.3 抖動轉移函數(Jitter Transfer, JTF)    8
1.4 抖動容忍度(Jitter Tolerance, JTOL)    9
2 傳統時脈與資料回復電路    10
2.1 鎖相迴路式時脈與資料回復電路[10]-[11]    10
2.2 混合鎖相迴路/延遲鎖相迴路式時脈與資料回復電路[12]-[13]    12
2.3 超取樣式時脈與資料回復電路[14]    13
2.4 相位選擇式時脈與資料回復電路[15]    14
3 四階脈波振幅調變時脈與資料回復電路之設計背景    15
3.1 四階脈波振幅調變資料    15
3.2 非歸零式資料與四階脈波振幅調變資料之差異性    16
3.3 減少回復時脈抖動之時脈與資料回復電路[16]-[20]    19
3.4 增加資料轉態密度之時脈與資料回復電路[21]    20
4 比較與討論    21
 第3章 具四階脈波振幅調變資料相位偵測與還原資料選擇之時脈與資料回復電路設計與實現    23
1 電路架構    23
2 系統分析    25
2.1 頻率資訊鎖相迴路系統分析    25
2.2 時脈與資料回復電路系統分析[6]    28
3 操作說明    34
3.1 四階脈波振幅調變資料之非理想現象    34
3.1.1 四階脈波振幅調變資料之上升時間與下降時間    34
3.1.2 四階脈波振幅調變資料之相位變化    36
3.1.3 四階脈波振幅調變資料之轉態密度    38
3.2 四階脈波振幅調變資料之抖動容忍度改善    38
4 行為模擬    41
5 子電路介紹    44
5.1 四階脈波振幅調變二進位相位偵測器    44
5.2 還原資料選擇電路    47
5.3 相位頻率偵測器    49
5.4 電荷幫浦    50
5.5 電壓控制振盪器    52
5.6 除頻器    54
5.7 擺幅轉換電路    55
6 模擬結果    56
6.1 佈局前模擬    57
6.2 佈局後模擬    59
6.3 抖動容忍度模擬    61
 第4章 晶片佈局與量測考量    63
1 電路佈局    63
1.1 晶片封裝    64
1.2 佈局與電源規劃    66
2 量測考量    67
2.1 量測環境    67
2.2 印刷電路板    68
2.3 高頻輸出緩衝器    69
2.4 低頻輸出緩衝器    70
2.5 高頻輸入端    71
3 規格比較表    72
 第5章 結論    75
1 結論    75
2 未來研究方向    75
參考文獻    76





                                

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