可見光通訊系統(Visible Light Communication，VLC)主要是透過LED照明設備發出肉眼無法察覺的高頻率明暗閃爍之可見光，在不影響日常照明的使用下同時傳遞資料訊息。本論文使用OFDM技術來減輕符際干擾(Inter Symbol Interference，ISI)等問題，在訊號編碼上使用QPSK。本篇所模擬VLC系統的取樣頻率為200MHz，其中OFDM使用64點的FFT，OFDM symbol的長度為360ns，我們模擬不同房間大小之系統效能，其中房間大小為(7.73 m, 6.6 m, 2.8 m)之系統效能在〖SNR〗_e = 15 dB時，系統之位元錯誤率(Bit Error Rate，BER)可達到10-5至10-6。由於基頻訊號是對光的強度作調變，在時域的訊號將只會是純實數，因此使用實係數之(Real FFT，RFFT)來降低運算量。
本論文提出RFFT的單路徑延遲回授(Single-path Delay Feedback，SDF)架構，利用Hermitian symmetry的共軛對稱特性將複數FFT的多餘頻域輸出訊號予以移除，以節省運算量和硬體複雜度。並根據實複數值混和路徑型態的訊號流程圖(Signal Flow Graph，SFG)來設計，主要原因除了增加硬體的使用率之外，也是為了降低複數型態延遲單元的數量。我們針對第三級的複數乘法運算做適當的重新排程，再搭配硬體共用的方式以更有效率地使用延遲單元。所提出的硬體使用了(4 log_2⁡N-6)個實數加法器、(log_8⁡N-3/2)個複數乘法器和(9N/8-1)個實數延遲單元，因此相較於其他RFFT的多路徑延遲交換(Multi-path Delay Commutator，MDC)架構以及CFFT的SDF架構，我們所使用的複數乘法器數目也相對的比較少。

Visible light communication (VLC) is an alternative of wireless communication and it transmits signals by LEDs illumination. In this paper, we modulate signals by OFDM technology to mitigate the inter symbol interference (ISI) caused by multipath effect and encode transmitted signals by QPSK. The sampling frequency is 200 MHz and the size of FFT and CP period is 64 point and 8 samples. Hence, the OFDM symbol period is 360 ns in the VLC system that we simulate. We simulate the VLC system in different room sizes. In the simulation of special room(7.73 m, 6.6 m, 2.8 m), a bit error rate (BER) of 10-5 to 10-6 is achieved under the 〖SNR〗_e = 15 dB. The OFDM baseband signal is used to modulate the LED intensity, and therefore the signals on the time domain will be only real value. Hence, we can use the real FFT (RFFT) to reduce operation.
This paper presents the single-path delay feedback (SDF) architecture for the FFT with real input samples. We take the advantage of Hermitian symmetry to save the computation and hardware complexity. The proposed N-point real FFT SDF architecture is based on the hybrid data-path SFG which is used to increase the hardware utilization and to reduce latency. With the proper scheduling in the stage 3 of the RFFT SDF architecture, we can use delay element efficiently by hardware sharing. Therefore, the proposed SDF architecture only requires (4 log_2⁡N-6) real adders, (log_8⁡N-3/2) complex multipliers and (9N/8-1) real delay elements. The hardware complexity is fewer than several real FFT multi-path delay commutator (MDC) architecture and complex FFT SDF architecture.

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