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研究生: 丁玄峰
Huasn-Feng Ting
論文名稱: 具多斜率展頻技術之低電磁干擾降壓轉換器
A Low EMI DC-DC Buck Converter with Multiple-Slopes Spread-spectrum Clock Technique
指導教授: 鄭國興
Kuo-Hsing Cheng
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 中文
論文頁數: 83
中文關鍵詞: 切換式穩壓器展頻技術降壓轉換器CISPR22
外文關鍵詞: DC–DC Converter, Spread-spectrum Clock Technique, Buck Converter, 國際無線電干擾 特別委員會
相關次數: 點閱:8下載:0
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  • 切換式穩壓器會產生傳導性的電磁干擾,在國際無線電干擾特別委員會將規範其電
    磁干擾量,故本論文提出一個輸入為1.8 V 輸出為1 V 的降壓轉換器、擁有兩種不同展
    頻模式之多斜率展頻技術之低電磁干擾降壓轉換器。在此設計中,本設計使用含有多頻
    率馳張震盪器,因此可在產生不同的頻率達到降低電磁干擾之功能。提出一個可切換斜
    率的展頻控制希望可以讓電磁干擾抑制效果更佳。使用不同斜率的展頻模式會產生不同
    的抑制效果,藉著比較不同的展頻模式得到一個良好的展頻效果。
    本論文之具多斜率展頻技術之低電磁干擾降壓轉換器使用180 nm 1.8 V CMOS 製
    程實現晶片,其操作頻率為1 MHz,並且擁有兩種展頻模式。電路在展頻範圍為1 MHz
    時三角波調變展頻機制對於電磁干擾之抑制量為10.96 dB,而使用三斜率展頻之電磁干
    擾抑制量為15.98 dB,展頻範圍為1.33 MHz 時三角波調變展頻機制對於電磁干擾之抑
    制量為16.35 dB,而使用三斜率展頻之電磁干擾抑制量為24.63 dB,整體晶片面積為1200
    × 1190 um2。


    A Low EMI DC-DC Buck Converter with Multiple-Slopes Spread-spectrum Clock Technique with 1 voltage output has been presented in this thesis. A multi- frequency relaxation oscillator with switching capacitor has been used in this design and this circuit can be operating at difference frequency. The proposed spread-spectrum clock technique can switch slop and generate multi-frequency. The triple slop mode used in the spread-spectrum mechanism increases the more reduction of electromagnetic interference with comparison to other modulations.
    The proposed A Low EMI DC-DC Buck Converter with Multiple-Slopes Spread-spectrum Clock Technique has been fabricated in 180 nm 1.8 V CMOS process. The reduction of electromagnetic interference are 16.35 dB with the spread-spectrum mechanism modulated by triangular mode 24.63 dB with the spread-spectrum mechanism modulated by triple slop mode. The chip area is 1200 × 1190 um2 .

    摘要 I Abstract II 誌謝 III 目錄 IV 圖目錄 VII 表目錄 X 第1章 緒論 1 1.1 研究動機 1 1.2 研究目的及其應用 2 1.3 論文架構 3 第2章 低雜訊切換式降壓穩壓器先前技術探討 5 2.1 電磁干擾(Ectromagnetic interference)簡介 5 2.2 展頻時脈產生器簡介 7 2.3 先前技術探討 8 2.3.1 利用跳頻降低電磁干擾之直流轉換器(Spur-Reduction Design of Frequency-Hopping DC–DC Converters)[3] 8 2.3.2 使用Delta–Sigma調變器之雜訊整型技術(A Noise-Shaped Switching Power Supply Using a Delta–Sigma Modulator)[4] 9 2.3.3 使用隨機切換頻率降低電磁干擾之轉換器(Random Switching Frequency Buck Converter for Conductive EMI Reduction)[5] 10 2.4 預計論文規格 12 第3章 低雜訊切換式降壓轉換電路設計 15 3.1 系統架構 15 3.2 小信號分析[6] 16 3.2.1 電壓模式模型分析 16 3.3 展頻控制電路(Spread-spectrum controller) 24 3.3.1 展頻機制 (Spread-spectrum) 24 3.3.2 馳張震盪器(Relaxation oscillator) 25 3.3.3 斜率選擇器 (Slope selector) 26 3.3.4 斜率偵測器 (Slope detector) 27 3.3.5 斜率切換器 (Slope switch) 28 3.3.6 上下數計數器 (Up/Down counter) 29 3.4 帶差參考電路 (Band gap reference) 30 3.5 誤差放大器(Error amplifier ) 32 3.6 比較器電路(Comparator circuit) 32 3.7 緩啟動電路(Soft start circuit) 33 第4章 行為模擬及參數分析 35 4.1 行為模擬架構圖 35 4.1.1 電磁干擾抑制量與展頻階數之關係 36 4.1.2 電磁干擾抑制量與斜率之關係 39 4.1.3 展頻參數之選擇 42 第5章 電路模擬與晶片量測結果 45 5.1 設計流程 45 5.2 佈局後電路模擬 45 5.2.1 帶差參考電路模擬結果 45 5.2.2 誤差放大器模擬結果 46 5.2.3 輸出漣波及其頻譜模擬 47 5.3 電路佈局 51 5.4 晶片照相與量測環境設定 54 5.5 量測結果 55 5.6 規格比較 62 第6章 結論與未來研究方向 65 6.1 結論 65 6.2 未來研究方向 65 參考文獻 67

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