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研究生: 林妤穎
Yu-ying Lin
論文名稱: 兼併切換式電容及切換式放大器且應用於生醫訊號之三角積分調變器
A Sigma-Delta modulator for Bio-signals Measurement System Combining Switched-Capacitor and Switched-OPAMP Technique
指導教授: 薛木添
Muh-tian Shiue
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 99
語文別: 中文
論文頁數: 81
中文關鍵詞: 切換式電容切換式運算放大器
外文關鍵詞: switched-opamp, switched-capacitor
相關次數: 點閱:4下載:0
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  • 近年來,憑藉著醫學與超大型積體電路的演進,常見的生理訊號量測儀器已朝向多功能、可攜式與高精準度發展。在量測系統中,除低雜訊生醫放大器外仍需一高精密度之類比數位轉換器將訊號正確地交由數位訊號處理模組進行資料處理與分析。因此,本論文中選擇三角積分調變器 (SDM) 之類比數位轉換器,其可降低前端類比濾波器設計之困難與功率消耗,進而減少整體量測系統面積。
    三角積分類比數位轉換器主要由三角積分調變器與數位降頻濾波器所組成。本文所設計之電路結合SC-SDM與SO-SDM之優點並將其整合,以低功率與高解析度為其設計標的完成一應用於所有生理訊號量測之三角積分調變器。電路實現上,在訊號頻寬10KHz、128倍超取樣率與±0.1V的輸入振幅下,所設計之二階三角積分調變器訊號雜訊失真比為70.5dB,有效位元數達到11.7位元且整體晶片消耗之功率為161μW。製作過程使用台積電0.18μm CMOS 1P6M製程,其晶片面積約佔1.035mm2。最後的量測結果顯示訊號雜訊失真比為46.2dB,有效位元數為7.7位元。在1.8V電源供應下,整體晶片消耗之功率約224μW。


    In recent years, public bio-signal measurement systems have been developed toward high accuracy, multi-functionality and portability due to the advancement of the medical science and VLSI technology. In addition to the bio-signal analog-front-end (AFE) circuits, measurement systems require a precision analog-to-digital (A/D) converter that can convert signals precisely to digital signal processing for analyzing data. Therefore, we choose the A/D converter which include Sigma-Delta modulator (SDM) to reduce anti-aliasing filter complexity and power consumption, resulting in reducing overall chip area of measurement systems.
    A Sigma-Delta A/D converter mainly consists of SDM and decimation filter. In this thesis, the proposed SDM combines the advantages of Switched-Capacitor SDM (SC-SDM) and Switched-OPAMP SDM (SO-SDM). The SDM aiming at low power consumption and high resolution is accomplished for all applications of bio-signal measurement. The modulator achieves 70.5dB signal-to-noise and distortion ratio (SNDR), 11.7 effective number of bits (ENOB) , and power consumption 161μW at 10-KHz signal bandwidth with an oversampling ratio (OSR) of 128, and 0.2Vp-p amplitude. The circuit is fabricated in the TSMC 0.18-μm one-poly six-metals CMOS process, and chip area is 1.035mm2. Finally, the measurement results show that signal to noise distortion ratio is 46.2dB, and 7.7 effective number of bits. The measured power consumption is about 224μW for 1.8V power supply.

    摘要 i Abstract ii 致謝 iii 目錄 iv 圖目錄 vi 表目錄 ix 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 2 1.3 論文架構 4 第二章 三角積分調變器原理介紹 5 2.1 奈奎斯特與超取樣類比數位轉換器 5 2.2 量化誤差 7 2.3 超取樣與雜訊移頻技術 9 2.3.1 超取樣技術 9 2.3.2 雜訊移頻技術 10 2.4 超取樣三角積分調變器 12 2.4.1 一階三角積分調變器 12 2.4.2 二階三角積分調變器 14 2.5 高階三角積分調變器 15 2.5.1 單迴路三角積分調變器 17 2.5.2 串接式高階三角積分調變器 17 第三章 切換式電容與切換式運算放大器之簡介 20 3.1 切換式電容積分器與切換式運算放大器積分器簡介 20 3.1.1 切換式電容積分器 20 3.1.2 切換式運算放大器積分器 23 3.2 二階切換式電容與切換式運算放大器之三角積分調變器系統簡介 25 3.2.1 二階切換式電容三角積分調變器 25 3.2.2 二階切換式運算放大器三角積分調變器 26 3.3 系統架構考量 29 第四章 三角積分調變器設計與模擬 32 4.1 電路系統非理想效應考量 32 4.1.1 熱雜訊 32 4.1.2 取樣雜訊 34 4.1.3 運算放大器之非理想效應 40 4.2 規格制定 42 4.3 系統設計 43 4.4 電路設計 45 4.4.1 運算轉導放大器 45 4.4.1 量化器與一位元數位類比轉換器 49 4.4.2 非重疊時脈產生電路 50 4.5 系統模擬結果 52 第五章 佈局與量測考量 56 5.1 佈局考量 56 5.2 量測考量 57 5.3 量測結果 59 第六章 結論與未來展望 62 6.1 結論 62 6.2 未來展望 63 參考文獻 64

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