本論文主要針對在高阻值矽(111)基板上進行氮化鋁/氮化鋁鎵/氮化鋁/氮化鎵電晶體製作與研究，希望藉由表面高溫氧化技術，使表面形成氮氧化鋁並與隨後沉積之閘極絕緣層形成更好的介面及較佳的絕緣層品質。
為了探討高溫氧化製程對介面缺陷密度以及閘極絕緣層的影響，本論文採用快速熱退火機台在環境溫度900 °C氧氣流量20 sccm下分別進行2、3.5、5 min不同時間的高溫氧化製程，接續沉積氧化鋁作為元件的閘極絕緣層，並進行450 ℃閘極絕緣層之熱退火，製作出金氧半電容。元件閘極漏電流，在逆偏狀態下最低可達10-6 A/cm2相較於未經高溫氧化製程的金氧半電容降低約2個數量級，藉由電容電壓量測，可觀察到高溫氧化製程能改善不同頻率間產生的散色現象，反應出氧化層與半導體間的介面缺陷密度獲得改善，約在1012~1013 cm-2eV-1。
更進一步的將此高溫氧化製程技術應用至金氧半場效電晶體的製作上，並進行特性比較，發現高溫氧化處理能夠降低電晶體的閘極漏電流，以及改善介面缺陷密度，但是卻可能造成緩衝層及元件側壁的漏電流提升。
本實驗同時對金氧半場效電晶體進行動態導通電阻量測分析，比較關閉狀態下不同的偏壓條件，結果發現在電晶體關閉狀態而汲極施加偏壓小於30 V時，相較於未進行高溫氧化處理的金氧半場效電晶體測得之動態電阻/穩態導通電阻比值是有改善的，但隨著汲極偏壓大於30 V時，動態特性劣化的情況較未進行高溫氧化處理的金氧半場效電晶體更為嚴重，此結果顯示元件的動態導通電阻不僅受到介面缺陷密度的影響，高電場作用下容易引發出緩衝層及磊晶層當中缺陷，進而影響元件的切換特性。

This study focuses on the fabrication and characterization of AlN/AlGaN/AlN/GaN HEMTs on high-resistivity Si（111）substrate. The thermal oxidation is proposed before gate dielectric deposition to achieve the high quality gate dielectric and lower interface state density.
To discuss the impact of the high temperature oxidation process, we fabricated the metal-oxide-semiconductor capacitor (MOS capacitor) with 10 nm Al2O3 gate dielectrics with thermal oxidation process. The thermal oxidation process was in O2 ambient at 900 C for 2、3.5、5 minutes before the gate dielectrics deposition, followed by post-deposition annealing（in N2 ambient at 450 C）. When MOS capacitors were reverse-biased, the MOS capacitor with thermal oxidation showed the lowest gate leakage current about 10-6 A/cm2, which is lower than the MOS capacitor without thermal oxidation by twofold. From capacitance–voltage measurement results, device with thermal oxidation process shows the lower dispersion between different measurement frequencies. The MOS capacitor with thermal oxidation process show the improvement on the interface state density between gate insulator and semiconductor. The interface state density is reduced to about 1012~1013 cm-2eV-1.
Comparing the influence about thermal oxidation process on MOS-HEMT. Devices with thermal oxidation process show reduction in the gate leakage current, and the interface state density. However, device with thermal oxidation process showed the lower buffer breakdown voltage.
In addition, dynamic resistances of the devices were analyzed with different kinds of quiescent bias. When drain quiescent bias is below 30V, the device with the thermal oxidation shows lower dynamic on-resistance to steady-state on-resistance ratio. When drain quiescent bias is High than 30 V, the device with the thermal oxidation shows the higher dynamic on-resistance to steady-state on-resistance ratio. The experimental results showed that the dynamic resistance is not only dominated by the interface density, but also affected by the buffer defects at high electric field.

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