摘 要
在系統單晶片的測試上，使用測試資料壓縮的方法來降低龐大的測試資料是一個相當有效的技巧。在這論文當中，我們提出一個多碼壓縮技術去壓縮系統單晶片中的測試資料。多碼壓縮技術中包含了多種不同連續長度編碼方法 (例如: 格倫編碼，頻率指向連續長度編碼，交替式連續長度編碼，…等。)。為達到提高壓縮率的目的，我們利用分割測試樣本的技巧首次被使用來分割一測試集合成為多個子測試集合，再將每一子測試集合個別使用適當的編碼方法壓縮。在實驗與分析結果中顯示，所提出的多碼壓縮技術相較於其他單一編碼壓縮的方法，在多數的測試集合中約提高20%的壓縮率。
相對於多碼壓縮技術，我們也同時提出一個用於解壓縮測試資料的基礎矽智產。若將包含6種解壓縮技巧的基礎矽智產應用於測試6個數位核心，其額外付出的面積僅有相當於360個邏輯閘的大小。最後，我們將所提出的基礎矽智產整合為一個產生器，此產生器會依照不同核心需求自動產生所需基礎矽智產的verilog RTL。

Abstract
Test data compression is one of useful techniques for reducing the volume of test data for system-on-chip (SOC) testing. In this paper, we propose a multi-code-compression technique to compress test data of SOCs. The multi-code-compression technique is composed of different compression techniques (e.g., Golomb, frequency-directed run-length, alternating run-length, etc.). To achieve high compression ratio, a test pattern partition technique is first used to partition a test into multiple subtests. Then each subtest can be compressed by an adequate code. Experimental and analysis results show that the proposed multi-core-compression scheme can achieve about 20% increment in compression ratio for most test benches compared with the single-code compression scheme. An infrastructure IP (IIP) for decompression of the compressed test data is also proposed. The area overhead of an IIP which consists of six methods for six cores is about 360 gates. An IIP Generator is implemented to generate RTL code of IIPs for different cases automatically.

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