論文內容提要
著眼於未來次世代電晶體元件的綠能微縮發展，量子穿隧式場效電晶體以穿隧效應產生電流，該電晶體僅需小操作電壓(約0.5 V)下即可進行工作。該元件有極佳的開關切換特性、低的次臨限擺幅、關閉時很低的漏電流與低功率損耗等優點。於矽基材半導體的穿隧電晶體開發中，有鑑於追求更低的功率損耗與操作偏壓，因III-V族半導體具有低能隙更容易產生穿隧機制獲得更低的操作偏壓。且III-V族材料有其可調控能帶接合之優點，故本論文著重於開發III-V族化合物半導體之穿隧式場效電晶體。
本論文所使用的磊晶結構為p-i-n摻雜的砷化銦鎵材料，其中銦的成分比例為53%，鎵的比例佔47%。在此砷化銦鎵的穿隧式場效電晶體結構中，為了達到穿隧機制須有p+重摻雜的源極與n+摻雜的汲極。本論文製作之磊晶晶片源極為p+型砷化銦鎵，其鈹元素摻雜其濃度為8 × 1018 /cm3，汲極部分矽元素摻雜濃度為1 × 1018/cm3，i層厚度為150 nm。
藉由濕式蝕刻穿隧式場效電晶體製程研發，以光學曝光製作微米尺寸元件，並改變氧化層材料參數。成功製作出汲極長度LD = 2 μm的元件，氧化鋁/氧化鉿EOT為2 nm，其次臨限擺幅為240 mV/dec，電流開關比達1.52 × 104，汲極導通電流為9.33 μA/μm。

The operation of the tunnel field effect transistors (TFETs) can be carried out with a small operating voltage (0.5 V or less). Advantages of TFETs include excellent switching characteristics, low subthreshold slope (S.S.), and low power consumption. Although Silicon based TFETs have been developed but the power consumption and operation of the bias are high due to large bandgap of Silicon materials. Because Indium based TFETs show a lower effective tunneling barrier height (Ebeff), which results in lower operating bias voltage. Therefore, Indium based TFETs are studied in this thesis.
For a typical p-i-n InGaAs material was used in this study, which is lattice matched to InP substrate., In order to achieve the tunneling operation of n-type TFET, a heavily doped p+-InGaAs is dedicated for source, n+-InGaAs is for drain, and undoped InGaAs is for channel. The tunneling junction for n-type TFET is located at the junction between p+ In0.53Ga0.47As (Be doping of 3.3 × 1019 /cm3) and undoped In0.53Ga0.47As. The channel is a 150 nm undoped In0.53Ga0.47As layer. The drain is a n+ In0.53Ga0.47As (Si doping of 1 × 1018 /cm3).
In this study, a wet etching method was applied to fabricate TFETs by exposing the InGaAs channel layer. Different materials were studied for insulators including SiO2 by PECVD and Al2O3/HfO2 by ALD. The n-TFET with best current and S.S. performance is a device with drain length of 2 μm and insulator of Al2O3/HfO2 (EOT of 2 nm). The characteristics of this device demonstrated the best S.S. of 240 mV/dec, on/off current ratio of 1.52 × 104 and maximum ON current of 9.33 μA/μm .

[1] Committee, I.R., "International Technology Roadmap for Semiconductors, " 2011 Edition. Semiconductor Industry Association.
[2] Iwai, H. "Future of nano CMOS technology." Symposium on Microelectronics Technology and Devices (SBMicro).. IEEE. 2013
[3] Wang, P.-F., et al., "Complementary tunneling transistor for low power application. "Solid-State Electronics, 48(12): p. 2281-2286. 2004.
[4] Mayer, F., et al. " Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. " in International Electron Devices Meeting,2008.
[5] Mookerjea, S., et al. "Experimental demonstration of 100nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications. " in Electron Devices Meeting (IEDM), 2009
[6] Zhao, H., et al., "Tunneling Field-Effect Transistors With an of 50 and a Subthreshold Swing of 86 mV/dec Using Gate Oxide. " Electron Device Letters, 31(12): p. 1392-1394. 2010.
[7] Bijesh, R., et al. "Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 NearBroken-gap Tunnel FET with ION=740μA/μm,GM=700μS/μm and GigahertzSwitching Performance at VDS=0.5V. "in Electron Devices Meeting (IEDM), 2013
[8] Li, R., et al., "AlGaSb/InAs tunnel field-effect transistor with on-current of 78 at 0.5 V. "Electron Device Letters, 33(3): p. 363-365. 2012.
[9] Dewey, G., et al. "Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing." in Electron Devices Meeting (IEDM), 2011
[10] Yu, T., et al., "In0. 53Ga0. 47As/GaAs0. 5Sb0. 5 Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics." Electron Device Letters, 34(12): p. 1503-1505.2013.
[11] Sze, S.M. and K.K. Ng, "Physics of semiconductor devices. "2006: John Wiley & Sons.
[12] 陳俊明, "次微米磷化銦/砷化銦鎵異質接面雙極性電晶體自我對準基極平台開發. "中央大學電機工程學系學位論文, 2013.
[13] 李慶泰, "集極在上氮化鎵/氧化鋅異質接面雙極性電晶體." 中央大學電機工程學系學位論文, 2007.
[14] Remashan, K., et al., "ZnO-based thin film transistors having high refractive index silicon nitride gate. "Applied Physics Letters, 91(18): p. 182101. 2007.
[15] Schlom, D.G. and J.H. Haeni, "A thermodynamic approach to selecting alternative gate dielectrics." MRS bulletin, 27(03): p. 198-204. 2002.
[16] Wilk, G.D., R.M. Wallace, and J. Anthony, "High-κ gate dielectrics: Current status and materials properties considerations." Journal of applied physics, 89(10): p. 5243-5275. 2001.
[17] Milojevic, M., et al.," Interfacial Chemistry of Oxides on III-V Compound Semiconductors, "in Fundamentals of III-V Semiconductor MOSFETs. Springer. p. 131-172. 2010.
[18] Bennett, B.R., et al., "Antimonide-based compound semiconductors for electronic devices: A review". Solid-State Electronics, 49(12): p. 1875-1895. 2005.