由於人們平均壽命逐漸提升，行動不便的老年人為了確保身體健康無虞，各種穿戴式生醫電子醫療儀器如雨後春筍般崛起，故本論文將以如何降低功耗與面積為訴求，來達到方便攜帶與電池續航更加長效之目的。
本論文由三部分所組成，第一部分為設計一個應於生醫訊號之連續時間(CT)三角積分類比數位調變器，相較於離散時間(DT)系統，可減緩硬體需求。並以一個運算放大器達到兩階積分效果，同時導入電流重複使用技術(Current-Reusing)，可以抑制其閃爍雜訊、熱雜訊以及功率消耗。
第二部分為設計一個低雜訊且低供應電壓的帶差參考電路，其產生之與溫度變異無關的穩定偏壓可供三角積分調變器當作回授偏壓以及其他各子電路使用。
在第三部分，由於CTDSM存在與溫度、製程變異嚴重的缺點，因此本論文加入RC時間常數校正機制，偵測並補償RC變異，確保調變器正常運作。最後再加入一個數位降頻濾波器，並整合成一個完整的連續三角積分類比數位轉換器。
本論文的電路設計均使用UMC 0.18 μm CMOS 1P6M製程。為了追求低功耗，因此將所有電路的供應電壓設定為1.2 V。第一部份的CTDSM設計在10 kHz頻寬、128倍超取樣率、0.3 V的輸入振幅，量測到的訊號雜訊失真比(SNDR)為78.42 dB，有效位元(ENOB)為12.73位元，功率消耗約為15.97μW，其晶片面積 (包含PAD & Seal-Ring)為0.67mm*0.56mm。第二部分的帶差參考電路輸出為0.6 V的穩定偏壓(可調式)，其模擬頻寬內之輸出總雜訊量為0.496 nV^2/(0.1~10 kHz)，功率消耗為17.3 μW。最後完整的CT Delta-Sigma ADC ，其模擬可達到的訊號雜訊失真比(SNDR)為80.31 dB，有效位元(ENOB)為13.05位元，功率消耗約為71.82 μW(調變器+帶差參考電路+RC時間常數校正電路+Buffer)，整體晶片佈局面積(包含PAD & Seal-Ring)為1.74mm*1.11mm。

With the increment of average age of people, various bio-medical wearable devices have been launched, especially for the elders. Therefore, how to reduce the power consumption and area to achieve the portability as well as the long battery life-time requirements are demands of this thesis.

This thesis consists of three parts, the first part designs a continuous-time delta-sigma modulator (CTDSM) for bio-medical application to ease the requirements of hardware rather than discrete-time DSM using an OPA to achieve the second-order integration. Besides, the current-reusing technique is used to maintain flicker noise and thermal noise to lower level and to keep low power consumption.

In the second part, a bandgap voltage reference (BGR) is introduced to meet low-noise and low supply voltage requirements. It can provide a stale voltage reference without the variation of temperature for feedback reference of DSM and other sub-circuits.

Third, the drawback of a CTDSM is the dependence on the variation of environment temperature and process. Therefore, the RC Time-Constant Calibration method is proposed for detecting and compensating the variation of RC time-constant. Finally, by introducing a decimation, we integrate all sub-circuits to a complete continuous-time delta-sigma ADC.

Designs in this thesis are fabricated in the UMC 0.18 μm 1P6M CMOS process. In order to pursue low-power consumption, the supply voltage is all set up as low as 1.2 V. First, the measurement of CTDSM achieves 78.42 dB SNDR, 12.73 bits ENOB, and power consumption 15.97 μW at 10 kHz signal bandwidth with X128 OSR, 0.6 Vp-p amplitude and chip area is 0.67mm*0.56mm, including PAD and seal-ring. Second, BGR generates a stable 0.6 V voltage reference which is tunable with flicker and thermal noise 0.496nV^2/(0.1~10 kHz) in the bandwidth for 17.3 μW. Finally, the simulation of the complete CT delta-sigma ADC achieves 81.31 dB SNDR, 13.21 bits ENOB, and power consumption 71.82 μW, including CTDSM, BGR, RC Time-Constant Calibration and buffers. The whole chip area is 1.74mm*1.11mm, including PAD and seal-ring.

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