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研究生: 楊鈞偉
Chun-Wei Yang
論文名稱: 具延遲處理器的空時碼之軟式輸入輸出遞迴解碼
Soft-Input/Soft-Output Iterative Decoding for Space-Time Coding With a Delay Processor
指導教授: 魏瑞益
Ruey-Yi Wei
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
畢業學年度: 93
語文別: 英文
論文頁數: 72
中文關鍵詞: 籬柵編碼調變延遲處理器軟式輸入輸出遞迴解碼多樣性空時碼
外文關鍵詞: space-time code, soft-input/soft-output (SISO) iterative decoding, trellis coded modulation, delay processor, diversity
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  • 在無線通道的編碼技術中,多樣性與編碼增益是影響錯誤效能的兩大重要因素。最近,結合具有延遲處理器的籬柵編碼調變與正交空時區塊碼的架構被提出,這個架構可以在窄頻的半平穩衰退通道與寬頻的正交分頻多工衰退通道中有效率的獲得全多樣性並且同時擁有好的編碼增益。之前對於這個架構所作的解碼是使用硬式輸出遞迴解碼,為了獲得更好的效能,在本篇論文中,我們使用軟式輸入輸出遞迴解碼,並將此架構與位元交錯編碼調變作比較。


    The diversity gain and coding gain are two important factors in wireless communications. Recently, the scheme that concatenates space-time block coding with trellis coded modulation with a delay processor is proposed, which can efficiently achieve the full diversity and also obtain good coding gain for the narrowband quasi-static fading channels and the wideband OFDM fading channels. The decoding way for this scheme was a hard-output iterative decoding previously. In order to further improve the error performance, we use the soft-input /soft-output iterative decoding in this thesis and compare it with the BICM scheme.

    1 Introduction 1 2 Reviews on Space-Time Coding and Trellis Coding with a Delay Processor 4 2.1 Space-time Coding 4 2.1.1 Diversity 5 2.1.2 Space-Time Block Coding 6 2.1.3 Space-Time Trellis Coding 8 2.2 Trellis Coded Modulation 11 2.3 Concatenated Space-Time Block Coding With Trellis Coded Modulation 13 2.4 Trellis Coding Structure with a Delay Processor and a Signal Mapper 15 2.4.1 Encoder 15 2.4.2 Hard Decoder 16 2.4.3 Soft Decoder 19 3 Space-Frequency Coded OFDM Systems for Frequency-Selective Channels 24 3.1 The OFDM System and SF Coded OFDM System Model 24 3.2 Concatenated Space-Time Block Coding with Trellis Coded Modulation for OFDM Systems 27 3.3 A New Scheme for Large Diversity 31 4 Soft-Input/Soft-Output Iterative Decoding for Space-Time Coding With a Delay Processor 34 4.1 Concatenated Space-Time Block Coding with A Delay Processor and A Signal Mapper 34 4.2 Simulation Results and Performance Analysis 37 5 Conclusions 69

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