由於類比元件的敏感性，以及製程技術的演進與元件尺寸的縮小，致使佈局後的電氣效應對於整體電路效能的影響日益加劇。為了減少電氣效應，類比設計大多以人工的方式產生佈局，雖然使用類比設計自動化搭配工程師的佈局經驗可以取代部分人工，但是眾多的佈局限制仍然使得類比設計自動化的發展無法被有效地突破。
目前存在許多類比元件擺置的相關文獻，然而同時考慮到繞線的研究卻非常稀少。在擺置的過程中，雖然可以利用拓樸限制幫助降低製程所造成的不匹配效應，但是繞線仍會對類比元件產生非預期的電氣效應。為了減少繞線所產生的電氣效應，最佳的繞線路徑必須避開類比元件，因此，在擺置的過程中必須要事先預留足夠的繞線空間，以確保繞線的路徑能夠避開類比元件。
本篇研究提出一個在擺置階段考量預留繞線空間的類比自動化設計流程。事先對繞線路徑做預估，以確保可產生能成功繞線的結果。並且將延遲決策技術擴充並應用於設計流程中，使設計流程能夠產生出符合對稱限制的結果。使用延遲決策技術除了可以產生非隨機性的結果，還能提供複數的結果以供工程師有更彈性的選擇。

Due to the sensitivity of analog components, the evolution of process technologies, and the size shrink of components, post-layout electrical effects increasingly impact the circuit performance. In order to reduce the electrical effects, the layouts of most analog designs are done by manual. Although layouts of partial designs can be done by EDA tools with experience of engineers, the development of analog design automation cannot be easily broken through due to a large number of layout constraints.
Although there are many literatures on analog placement, the number of researches on analog placement considering routing is few. In the placement process, although we can use the topology constraints to reduce the mismatch, the unexpected electrical effects will be produced by the routing paths. In order to reduce the electrical effects produced by the routing paths, routing paths must avoid the analog devices, implying that enough routing spaces are needed to be preserved in the placement stage.
This work presents an analog placement flow to handle the symmetry constraints, and to preserve enough routing spaces between devices. The flow is based on the deferred decision making (DDM) technique. Using DDM technique cannot only generate non-stochastic solutions, but also provide multiple and flexible solutions for engineers.

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