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研究生: 黃佳淳
Jia-Chun Huang
論文名稱: 應用於數位視頻廣播系統中之自動增益放大器
Automatic Gain Control and Continuous-Time Receive Filter in DVB-T/H Receiver Design
指導教授: 薛木添
Muh-Tian Shiue
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度: 94
語文別: 英文
論文頁數: 70
中文關鍵詞: 濾波器自動增益放大器數位視頻廣播系統
外文關鍵詞: DVB-T/H, AGC, Filter
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  • 在本論文中,描述一個類比前端電路,主要是以基頻接收端通訊系統應用為目標,應用在數位視頻廣播系統中。內包含一個經由數位控制的自動增益放大器和一個抗混淆濾波器。在接收端的信號路徑上包含一個可程式化增益放大器,這個類比的放大器擁有51dB 的動態增益範圍,並且由一階的數位控制迴路來自動調整其增益量。使其輸出可到達160mVpp。在輸入震幅也是160mVpp 的情況下,經由
    雙端輸入模擬出的全諧波失真(THD)小於 -60dB。此設計已使用台灣積體電路公司所提供 0.18 微米 CMOS 製程製作。操作在1.8V 電壓下,消耗功率為13 毫瓦。緊接著這個自動增益放大器是一個頻寬為4MHz 的五階Chebyshev 低通濾波器,此外一個運算跨導放大器(OTA)將被運用在這個濾波器中。輸入震幅為160mVpp模擬出的全諧波失真(THD)小於 -60dB。操作電壓在1.8V,此電路將被驗證在佈局後(post-layout)的模擬上。


    This paper describes a digitally controlled automatic gain control (AGC) and anti-aliasing
    filter subsystems for the analog front-end (AFE), in which it can be used to support the digital video broadcasting in DZIF (double conversion with zero second IF) architecture. The receiving path contains a programmable-gain amplifier (PGA) with the self-tuning gain circuit. The dynamic range of the PGA, which is controlled by a digital loop to form a first order system, is 51dB. The third-harmonic distortion is less than -60dB for differential input signal up to 160mVpp. This chip has already been fabricated in a TSMC 0.18μm standard CMOS technology while the supply voltage is 1.8V and its power consumption is 13mW. Following the proposed AGC, a 4-MHz fifth-order Chebyshev low-pass Gm-C filter is also described in detail. In addition, an operational transconductance amplifier (OTA) with an additional enhanced amplifier structure is utilized to perform the voltageto-current conversion. The THD is less than -60dB over the input range of 160mVpp and the supply voltage is 1.8V. This proposed filter has also been completely verified by the post-layout simulation.

    Abstract iv Acknowledgments v List of Tables ix List of Figures x Chapter 1 Introduction 1 1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 2 System Architectures and Design 4 2.1 Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 Low-IF Receiver Architecture . . . . . . . . . . . . . . . . . . . . . 5 2.1.3 Zero-IF Receiver Architecture . . . . . . . . . . . . . . . . . . . . . 8 2.1.4 Double Conversion Zero-IF Architecture with DVB-T/H . . . . . . 12 2.2 Receiver Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Signal Control Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Proposed Digital Feedback AGC . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.1 Gain Control Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 First Order Approximation Analysis . . . . . . . . . . . . . . . . . 19 2.5 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chapter 3 Programmable-Gain Amplifier Design 23 3.1 Introduce PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Inverting and Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . 25 3.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1 Current Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2 Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.3 Variable Input Resistors . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.4 Common Mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.5 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4 VLSI Implementation and Simulation Result . . . . . . . . . . . . . . . . . 35 3.4.1 Layout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 4 Anti-Aliasing Filter Design 41 4.1 Introduce OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.1 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.2 Operation Transconductance Amplifier . . . . . . . . . . . . . . . . 48 4.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 5 Conclusion and Future Works 51 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Bibliography 53

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