| 研究生: |
施玟旭 Wen-hsu Shih |
|---|---|
| 論文名稱: |
三維空間環繞式閘極電晶體之模擬級分析 Analysis and simulation of 3-D Gate-All-Around Transistor |
| 指導教授: |
蔡曜聰
Yao-Tsung Tasi |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 中文 |
| 論文頁數: | 57 |
| 中文關鍵詞: | 環繞式閘極 、環繞式閘極電晶體 |
| 外文關鍵詞: | GAA, Gate-All-Around MOSFET |
| 相關次數: | 點閱:12 下載:0 |
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本篇論文中,我們將探討如何利用三維元件模擬器進行環繞式閘極電晶體的元件性模擬。利用環繞式閘極本身的特性,做四分之一等效切割,在不影響元件本身特性下進行模擬且大幅提升模擬速度。接著透過這樣的模擬方式,我們改變環繞式閘極電晶體其通道面積,分析通道內形成部分空乏及完全空乏之現象,討論這樣的現象對環繞式閘極之臨限電壓影響。最後分析環繞式閘極應用於無接面通道與傳統通道之特性比較,介紹兩種通道的操作原理,進而分析兩種通道如何選用Poly-Gate,最後改變各參數觀察對兩種通道的影響程度。
In this thesis, we use the three-dimensional device simulation to simulate the gate-all-around MOSFET device characteristics. Using the gate-all-around MOSFET characteristics, we cut the full device into one fourth device to speed up the simulation. Then ,we study the dependance of threshold voltage on the substrate thickness in the gate-all-around MOSFET. At last , we analyze characteristics of the junctionless MOSFET and conventional MOSFET. The basic operating principles of the two MOSFETs will be compared. We discuss how to choose poly-gate type on these two MOSFETs. Finally, we change the parameters to study the impact to these two MOSFETs.
[1] D. Grant, “Power semiconductor devices-continuous development,” Microelectronics Journal, Volume 27, Issues 2-3 , pp. 161-176, March-June 1996.
[2] J. T. Park, J. P. Colinge, and C. H. Diaz,“Pi-Gate SOI MOSFET”IEEE Electron Devices Letters, VOL. 22, no. 8, August 2001.
[3] J. P. Colinge, M. H. Gao, A. Romano, H. Me and C. Claeys,“Silicon-on-Insulator Gate-All-Around MOS Device,”IEEE Transaction on Electron Devices, 1990, PP. 137-138.
[4] T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y.Takahashi, and K. Murase,“Ultimately thin double-gate SOI MOSFETs,”IEEE Transaction on Electron Devices, Volume:50 Issue:3 , March 2003,P.830-838.
[5] D. I. Moon, S. J. Choi, J. P. Duarte, and Y. K. Choi, “Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate” IEEE Transaction on Electron Devices, VOL. 60, NO. 4, APRIL 2013
[6] D. M. Bressoud, “Appendix to A Radical Approcch to Real Analysis,” 2nd edition,2006
[7] D. A. Neamen,“Semiconductor physics and devices,”3rd ed., McGraw-HillCompanies Inc., p536, 2003.
[8] B. P. Wong, A. Mittal, Y. Cao, and G. Star,“Nano-CMOS circuit and physical design,”by John Wiley and Son Inc., pp. 41-42, 2005.
[9] J. G. Fossum et al,“Suppression of Corner Effects in Triple-Gate MOSFETs,”IEEE Electron Device Letters, vol. 24, pp. 745-747, Dec 2003.