可重構之高速奇異值分解處理器｜國立中央大學博碩士論文系統

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研究生：	陳信彰 Hsin-Chang Chen
論文名稱：	可重構之高速奇異值分解處理器 Design of Reconfigurable High Speed SVD Processor
指導教授：	薛木添 Muh-Tian Shiue
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	中文
論文頁數：	62
中文關鍵詞：	多天線多輸出系統、波束成型、奇異值分解
外文關鍵詞：	MIMO, Beamforming, svd
相關次數：	點閱：15 下載：0
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近年來，MIMO (Multi-Input Multi-Output,多輸入多輸出)系統越來越受到重
視，不僅因為多天線技術能夠有效的增加系統的吞吐率，應用多天線的技巧也能
提升系統的效能，但也必須處理各種傳輸端對接收端之天線數目不同所帶來的問
題，本論文以波束成型(Beamforming)常用的預編碼技巧SVD (Singular Value
Decomposition, 奇異值分解)之硬體實現為目標，設計一可支援1 × 1~4 × 4之任
意天線組合之SVD 處理器，為了減少傳統Memory-Based 架構所必須增加的時
序延遲，我們使用一暫存器陣列來取代實際的記憶體，並且設計一能夠配合演算
法做管線化的架構做硬體實現，所提出之設計除了能夠對應任意天線組合之外，
在面積、運算時間與功率消耗上也有相當的改善。本論文以SMIMS VeriEnterprise
Xilinx FPGA 驗證電路功能，最後利用TSMC-90nm 製程實現所設計之電路。

In recent years, it is more important to use MIMO (Multi-Input Multi-Output)
systems. MIMO techniques not only increase system throughput but also improve
system performance such as BER (Bit Error Rate). Due to different configurations
of antennas between transmitter and receiver, there are a few issues to be solved. SVD
(Singular Value Decomposition) is a common used precoding technique for
beamforming, and as the design target of implementation in this thesis. This thesis
proposes a reconfigurable architecture which can compute the SVD of 1 × 1~4 × 4
antenna configurations’ channel matrices. For reducing the clock delay lead of
conventional memory-based architecture, this thesis employs register arrays to replace
the real memory, and implements the GR-SVD algorithm by a pipelined circuit design.
The design results improve not only on throughput, but also the advantages of low
power and small area in chip implementation. The proposed configurable SVD
processor is function-verified by the SIMIS VeriEnterprise Xilinx FPGA development
board. Besides, the proposed architecture is also implemented in TSMC-90nm for
demonstrating the achievement of throughput, low power and small area.

摘要................................................................................................................................ i
Abstract ......................................................................................................................... ii
致謝.............................................................................................................................. iii
目錄............................................................................................................................... iv
圖目錄.......................................................................................................................... vii
表目錄........................................................................................................................... ix
第一章 緒論............................................................................................................ 1
1 系統介紹.................................................................................................... 1
1.1 MIMO 系統模型 ........................................................................... 1
1.2 模擬環境........................................................................................ 2
2 研究動機.................................................................................................... 3
3 論文架構.................................................................................................... 4
第二章 SVD 相關演算法 ...................................................................................... 5
1 Householder 變換 ...................................................................................... 5
2 平面旋轉.................................................................................................. 6
2.1 Givens Rotation ............................................................................. 6
2.2 CORDIC ........................................................................................ 7
3 Jacobi SVD 演算法 .................................................................................. 9
4 二對角化分割征服(Bidiagonal Divide-And-Conquer)演算法 .............. 11
5 各演算法之比較...................................................................................... 12
第三章 GRSVD 演算法....................................................................................... 13
1 二對角化矩陣.......................................................................................... 13
2 位移QR 與Wilkinson Shift .................................................................... 15
3 Chasing .................................................................................................... 17
v
3.1 Chasing ............................................................................................... 17
3.2 收斂判定與矩陣分割......................................................................... 18
第四章 GRSVD 之硬體電路設計 ...................................................................... 24
1 SVD 硬體架構......................................................................................... 24
2 暫存器陣列之電路設計.......................................................................... 26
3 CORDIC 之電路設計 ............................................................................. 28
3.1 CORDIC 之基本電路設計 ......................................................... 28
3.2 環形管線化CORDIC 之電路設計 ............................................ 30
4 Bidiagonalization Controller 之電路設計 ............................................... 33
4.1 BDC 之基本電路設計 ................................................................ 33
4.2 Data Hazard 之考量與設計 ........................................................ 35
5 Wilkinson Shift Calculator 之電路設計 ................................................. 37
5.1 WSC 之電路設計 ........................................................................ 37
5.2 Overflow 之避免 ......................................................................... 40
6 Chasing Controller 之電路設計 .............................................................. 41
6.1 CC 之電路設計 ........................................................................... 41
6.2 Chasing 之Data Hazard .............................................................. 43
7 Data Bus 之電路設計 .............................................................................. 44
8 Global FSM Controller 之電路設計 ....................................................... 45
第五章 晶片實現.................................................................................................. 46
1 設計流程.................................................................................................. 46
2 定點數分析.............................................................................................. 47
3 FPGA 驗證 .............................................................................................. 52
4 晶片設計結果............................................................................................... 54
4.1 模擬結果驗證.............................................................................. 54
vi
4.2 晶片結論...................................................................................... 57
5 硬體比較....................................................................................................... 59
第六章 結論.......................................................................................................... 60
參考文獻...................................................................................................................... 61
                                

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62
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