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研究生: 陳亭維
Ting-Wei Chen
論文名稱: 以RFSoC平台設計與實現高吞吐量DVB-S2 載波頻率同步與訊框同步器
Design and Implementation of High Throughput DVB-S2 Carrier Frequency Synchronizer and Frame Synchronizer with RFSoC Platform
指導教授: 陳逸民
Yih-Min Chen
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
論文出版年: 2023
畢業學年度: 112
語文別: 中文
論文頁數: 103
中文關鍵詞: 第二代數位衛星廣播都普勒效應載波頻率同步訊框同步數位訊號處理軟體定義無線電高吞吐量接收機現場可程式化邏輯閘陣列射頻系統晶片
外文關鍵詞: DVB-S2, Doppler Effect, Carrier Frequency Synchronizer, Frame Synchronizer, Digital Signal Processor, Software Defined Radio, High Throughput, Receiver, FPGA, RFSoC
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  • 低軌道通訊的技術蓬勃發展下,數位衛星廣播系統成不可或缺的關鍵。衛星在高
    速移動的情況下與地面站所產生之都普勒頻率偏移成為重要的課題,也因應高通量資料
    率串流的通訊技術,DVB-S2 相較於前一代有更好的傳輸量,支援 8PSK、16APSK、
    32APSK,使得在不同訊雜比(SNR)下能選擇更有效益的調變與碼率。
    本論文針對 DVB-S2 接收端之載波頻率同步與訊框同步的硬體架構設計與實現,
    探討其性能。載波頻率同步使用差分頻率估測器(Differential Frequency Estimator)、導向
    決策器(Decision-Directed)與迴路濾波器(Loop Filter)計算與修正頻率偏移,訊框同步包
    含 MODCOD 偵測器(MODCOD Detector)、抓取訊號及相位修正、訊框彈性器(Frame
    Elasticizer)與實體層解攪亂器(PL Descrambler)。


    With the flourishing development of Low Earth Orbit (LEO) communications technology,
    digital video broadcasting systems for satellite (DVB-S) have become indispensable. The
    Doppler effect generated when satellites are in rapid motion relative to ground stations has
    become a crucial issue. In response to high-throughput data rate streaming communication
    technology, DVB-S2 offers improved throughput compared to the previous generation. It
    supports 8PSK, 16APSK, and 32APSK, allowing for the selection of more efficient modulation
    and coding schemes under different signal-to-noise ratios (SNR).
    In this thesis, it focuses on the hardware architecture design and implementation of carrier
    frequency synchronization and frame synchronization for DVB-S2 receivers, along with a
    performance evaluation. Carrier frequency synchronization includes a Differential Frequency
    Estimator, Decision-Directed Phase Estimator, and Loop Filter to compute and correct
    frequency offsets. Frame synchronization includes MODCOD Detector, signal catcher and
    phase correction, Frame Elasticizer, and Physical Layer Descrambler.

    摘要......................................................................................................................................... i ABSTRACT.......................................................................................................................... ii 謝誌....................................................................................................................................... iii 目錄....................................................................................................................................... iv 圖目錄................................................................................................................................. viii 表目錄.................................................................................................................................. xii 第一章、 緒論................................................................................................................. 1 1.1 研究動機和背景..................................................................................................... 1 1.2 論文架構................................................................................................................. 1 第二章、 DVB-S2 收發機系統 ...................................................................................... 2 2.1 DVB-S2 發射端流程圖 .......................................................................................... 2 2.2 Stream Adaptation ................................................................................................... 3 2.2.1 Baseband Header insertion .............................................................................. 3 2.2.2 Padding ............................................................................................................ 4 2.2.3 Baseband Scrambling ...................................................................................... 5 2.3 Forward Error Correction Encoding........................................................................ 6 2.3.1 BCH Encoder................................................................................................... 7 2.3.2 LDPC Encoder................................................................................................. 8 2.3.3 Bit Interleaver.................................................................................................. 8 2.4 Bit Mapper............................................................................................................. 10 2.4.1 QPSK............................................................................................................. 10 2.4.2 8PSK.............................................................................................................. 10 2.4.3 16APSK......................................................................................................... 11 2.4.4 32APSK......................................................................................................... 12 2.5 Physical Layer Framing......................................................................................... 13 v 2.5.1 Dummy PLFRAME Insertion ....................................................................... 13 2.5.2 PL Signalling................................................................................................. 14 2.5.2.1 SOF field .......................................................................................... 14 2.5.2.2 MODCOD field................................................................................ 14 2.5.2.3 TYPE field ....................................................................................... 14 2.5.2.4 PLS Code ......................................................................................... 15 2.5.3 PL Scrambler................................................................................................. 16 2.6 基頻濾波器與發射端........................................................................................... 17 2.7 基頻接收端........................................................................................................... 19 第三章、 載波頻率同步............................................................................................... 21 3.1 載波頻率及相位偏差........................................................................................... 21 3.2 載波頻率同步器(Carrier Frequency Synchronizer)............................................. 24 3.2.1 差分頻率估測器(Differential Frequency Estimator) ................................... 26 3.2.2 導向決策(Decision-Directed) ....................................................................... 27 3.2.2.1 QPSK Hard-Decision Boundary ...................................................... 27 3.2.2.2 8PSK Hard-Decision Boundary ....................................................... 28 3.2.2.3 16APSK Hard-Decision Boundary .................................................. 29 3.2.2.4 32APSK Hard-Decision Boundary .................................................. 30 3.2.3 迴路濾波器(Loop Filter) .............................................................................. 30 第四章、 訊框同步....................................................................................................... 31 4.1 自動偵測器(MODCOD Detector)........................................................................ 32 4.1.1 MODCOD Correlator.................................................................................... 32 4.1.2 MODCOD Comparator ................................................................................. 33 4.1.3 MODCOD Peak Detector.............................................................................. 33 4.2 PLHeader 移除器(PLHeader Remover)................................................................ 34 4.3 訊框彈性器(Frame Elasticizer) ............................................................................ 34 vi 4.4 實體層解攪亂器(PL Descrambler) ...................................................................... 35 第五章、 硬體架構實現............................................................................................... 36 5.1 載波頻率同步器架構........................................................................................... 36 5.1.1 Differential Frequency Estimator.................................................................. 38 5.1.2 Decision-Directed Phase-Error Estimator ..................................................... 39 5.1.3 Loop Filter..................................................................................................... 40 5.2 訊框同步器架構................................................................................................... 41 5.2.1 MODCOD Detector....................................................................................... 42 5.2.1.1 PLS Correlator ................................................................................. 43 5.2.1.2 PLS Comparator............................................................................... 44 5.2.1.3 SOF Correlator................................................................................. 44 5.2.2 PLHeader Remover ....................................................................................... 45 5.2.3 Frame Elasticizer........................................................................................... 45 5.2.4 PL Descrambler............................................................................................. 47 第六章、 性能模擬分析............................................................................................... 48 6.1 載波頻率同步分析............................................................................................... 49 6.1.1 Loop Filter 參數分析 .................................................................................... 49 6.1.2 Differential Frequency Estimator 性能分析 ................................................. 54 6.1.3 載波頻率同步分析....................................................................................... 56 6.2 訊框同步分析....................................................................................................... 57 6.2.1 MODCOD Detector....................................................................................... 57 6.2.2 Frame Elasticizer........................................................................................... 59 第七章、 軟體定義無線電與硬體整合驗證............................................................... 60 7.1 軟體定義無線電................................................................................................... 60 7.2 RFSoC 平台........................................................................................................... 60 vii 7.2.1 DAC 與 ADC ................................................................................................ 61 7.2.2 Clock.............................................................................................................. 63 7.2.3 Nyquist Zone ................................................................................................. 64 7.2.4 DAC 與 ADC 資料擺放................................................................................ 65 7.2.5 DAC 與 ADC 操作介面................................................................................ 68 7.2.6 平台使用流程............................................................................................... 69 7.3 平台驗證............................................................................................................... 71 7.3.1 接收機整合................................................................................................... 71 7.3.2 硬體資源使用率........................................................................................... 72 7.3.2.1 載波頻率同步器.............................................................................. 72 7.3.2.2 訊框同步器...................................................................................... 73 7.3.2.3 接收機.............................................................................................. 74 7.3.3 接收機硬體實現結果................................................................................... 75 7.3.2.1 自發自收.......................................................................................... 76 7.3.2.2 一發一收.......................................................................................... 77 7.3.2.3 針對自發自收調整接收載波頻率.................................................. 78 7.3.2.3 Ka-band 一發一收........................................................................... 82 第八章、 結論............................................................................................................... 85 參考文獻.............................................................................................................................. 86

    [1] Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and
    modulation systems for Broadcasting, Interactive Services, News Gathering and other
    broadband satellite applications; Part 1: DVB-S2, ETSI EN 302 307-1 V1.4.1, ETSI, 2014.
    [2] Y.-M. Chen, “On the design of farrow interpolator for ofdm receivers with asynchronous if
    sampling,” in Communications and Networking in China, 2009.
    [3] Y.-M. Chen, “A simple carrier synchronization for dvb-s2 signals using polar decisiondirected phase error estimator,”, 2014.
    [4] Y.-J. LUO, “Design and Implementation of DVB-S2 Receiver with FPGA.”, National Central
    University, 2015.
    [5] P.-H. Chen, “Design and Implementation of DVB-S2 Transceiver with ACM function on
    SDR”, National Central University, 2022.
    [6] Zae Yong Choi and Yong H. Lee, “Frame Synchronization in the Presence of Frequency
    Offset”, 2002.
    [7] Guan-Ciou Huang “Implementation of Wideband OFDM mmWave Transceiver with RFSoC
    Platform. , National Central University Master’s thesis, Oct, 2020.
    [8] Y.-J. Lin, “Implementation of Multi-mode Wideband OFDM mmWave Transceiver and
    Application with RFSoC Platform”, National Central University, 2021.
    [9] U. Mengali, “Synchronization techniques for digital receivers.” Springer Science & Business
    Media, 1997.
    [10] Xilinx(2018, Decdmber 5). Zynq UltraAcale+ RFSoC RF Data Converter Evaluation
    Tool(ZCU111) User Guide. Retrieved from
    https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-
    eval-bd.pdf
    [11] Xilinx(2018, April 17). Zynq UltraScale+ RFSoC RF Data Converter 2.0 LogiCORE IP
    Product Guide. Retrieved from
    https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2
    _0/pg269-rf-data-converter.pdf
    87
    [12] Arm Developer. AMBA 4 AXI4-Stream Protocol Specification. Retrieved from
    https://developer.arm.com/documentation/ihi0051/a?lang=en
    [13] E. Casini, R. De Gaudenzi and A. Ginesi, “DVB-S2 modem algorithms design and
    performance over typical satellite channels”, Int. J. Satell. Commun. Network. 2004; 22:281–
    318.
    [14] A-INFO. Standard Gain Horn Antenna: LB-28-20-C-XX. Retrieved from
    http://www.ainfoinc.com.cn/en/pro_pdf/new_products/antenna/Standard%20Gain%20Horn
    %20Antenna/tr_LB-28-20.pdf
    [15] ANALOG DEVICES. ADNV1013: 24GHz to 44GHz, Wideband, Microwave Upconverter.
    Retrieved from
    https://www.analog.com/en/products/admv1013.html
    [16] ANALOG DEVICES. ADMV1014: 24GHz to 44GHz, Widebnd, Microwave
    Downconverter. Retrieved from
    https://www.analog.com/en/products/admv1014.html
    [17] Mini-Circuits ZVE-323LN-K+: 18 to 32GHz Wideband Amplifier. Retrieved from
    https://www.minicircuits.com/pdfs/ZVE-323LN-K+.pdf

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