本論文使用65奈米元件來探討偏壓和製程被變化時，在通道內的低頻雜訊的表現。汲極偏壓和閘極偏壓可被發現能夠分別的控制水平電場和垂直電場。因此，載子的速率和載子的遷移率將可被汲極和閘極的偏壓來改變。
當元件的通道被縮短時，當電壓被操作在臨界電壓附近，則低頻雜訊將有明顯的變化，短通道效應變的更為明顯。因此，低頻雜訊的變化可由基極的電壓來調整。當VSB被偏壓在0.5 V時，則低頻雜訊會被增加。相對的，當VSB被偏壓在-0.5 V時，則低頻雜訊會被降低。
雜訊的來源於二氧化矽與矽之間的懸浮鍵，此現象也可以稱為缺陷。缺陷可被特定的製程步驟來移除。我們發現在溫度1080 °C的nitridated gate oxide呈現很好的雜訊值數。用H2 annealing在溫度為425 °C呈現很好的雜訊值數。
口袋植入會沿著通道而創造不均勻的臨界電壓分佈。可發現有口袋植入的低頻雜訊會比沒口袋植入的來得高。相對的，在有口袋植入的Id-Vgs特性會顯現出好的次臨界電壓擺幅，尤其在短通道長度。在長通道長度沒有響影到Id-Vgs特性或低頻雜訊。

This thesis focuses on the low-frequency noise performance in a channel using a 65nm device when the bias and process is varied. The drain bias and gate bias was found to be able to control the horizontal electric field and vertical electric field, respectively. Therefore, the carrier velocity and carrier mobility are changed by the drain and gate bias.
As the channel size was reduced, clear variations appeared in the low-frequency noise when the device operated near the threshold voltage. The short channel effect became more evident. Therefore, the low-frequency noise can be varied by the bulk voltage. The low-frequency noise increased when the VSB was biased at 0.5 V. By contrast, the VSB was biased at -0.5 V so that the low-frequency noise could be reduced.
The noise stems from the dangling bond in the SiO2-Si interface. This phenomenon is also called a defect. The defect can be removed by specific fabrication processes. We found that the nitridated gate oxide has the best normalized noise power density when the temperature was 1080 °C. The H2 annealing showed the best normalized power density when the temperature was 425 °C.
The halo implant can be used to create the non-uniform threshold voltage distribution along the channel. The low-frequency noise with the halo implant was higher than without the halo implant in a short channel. By contrast, the Id-Vgs characteristics with the halo implant show a better sub-threshold swing and off-state current than without the halo implant, especially in the short channel. The long channel had no impact on the Id-Vgs characteristics or the low-frequency noise.

[1] H. Craig Casey, jr., “Device For Integrated Circuits – Silicon and III-V Componund Semiconductors,” John Wiley &Sons
[2] Martin von Haartman and Mikael Östling, “Low-Frequency Noise in Advance MOS Devices,” 2007 Springer
[3] Ali Hajimiri and Thomas H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, February 1998
[4] Giuseppe Bertuccio and Stefano Caccia, “Noise Minimization of MOSFET Input Charge Amplifiers Based on Δµ and ΔN 1/f Models” IEEE Trans. on Unclear Science, vol. 56, no. 3, pp. 1511-1520, June 2009
[5] Kwok K. Hung, “A Unified Model for the Flicker Noise in Metal-Oxide-Semiconductor Field-Effect Transistors” IEEE Trans. on Electron Devices, vol. 37, no. 3, pp. 654-665, March 1990
[6] S. Christensson, I. Lundstrom, and C. Svensson, “Low frequency noise in MOS transistors-I Theory,” Solid-State Electron, vol. 11, no. 9, pp. 797-812, 1968
[7] A van der Ziel, “Noise in Solid State Devices and Circuits,” New York: Wiley, 1986
[8] A van der Ziel, “Flicker noise in electronic devices,” advances in Electronics and Electron Physics, vol. 49, L. Marton, Ed. New York: Academic, 1979
[9] ProPlus design solution Inc., “9812B-User-Manual,”
[10] Neamen, Donald A., “Semiconductor Physics and Devices: Basic Principles,” McGraw-Hill, 2002
[11] N. Park and K. K. O, “Body bias dependence of 1/f noise in NMOS transistors from deepsubthreshold to strong inversion,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 999-1001, 2001
[12] M. J. Deen and o. Marinov, “Effect of forward and reverse substrate biasing on low frequency noise in silicon PMOSFETs,” IEEE Trans. on Electron Devices, vol. 49, no. 3, pp. 409-413, 2002
[13] M. von Haartman, B. G. Malm, and M. Östling, “Comprehensive study on low-frequency noise and mobility in Si and SiGepMOSFETs with high-k gate dielectrics and TiN gate” IEEE Trans. Electron on Devices, vol. 53, no. 4, pp. 836-543, 2006
[14] M. Marin, M. J. Deen, M. de Murcia, P. Linares, and J. C. Vildeuil, “Effects of body biasing on the low frequency noise of MOSFETs from 130 nm CMOS technology” IEEE Proceedings- Circuits, Devices and Systems, vol. 151, no. 2, pp. 95-101, 2004
[15] M. von Haartman, A.-C.Lindgren, P.-E Hellström, b. G. Malm, S.-L. Zhang, and M. Östling, “1/f noise in Si and 〖Si〗_0.7 〖Ge〗_0.3 pMOSFETs” IEEE Trans. on Electron Devices, vol. 50, no. 12, pp. 2513-2519, 2003
[16] Jun-Wei Wu, “Pocket Implantation Effect on Drain Current Flicker Noise in Analog nMOSFET Devices,” IEEE Trans. on Electron Devices, vol. 51, no. 8, pp. 1262-1266, August 2004
[17] VikramChaturvedi, BharadwajAmrutur, “A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS technology,” 2011 24th International Conference on VLSI Design, pp. 328-333, January 2011
[18] HidemiTsuchida, “Characterization of White and Flicker Frequency Modulation Noise in Narrow-Linewidth Laser Diodes,” IEEE Photonics Technology Letters, vol. 23, no. 11, pp. 727-729, March 2011
[19] L. B. Mercer, “1/f frequency noise effect on self-heterodyne linewidth measurements,” Journal of Lightwave Technology, vol. 9, no. 4, pp. 485-493, April 1991
[20] Daniel L. Creedon, “High-Resolution Flicker-Noise-Free Frequency Measurements of Weak Microwave Signals,” IEEE Trans. on Microwave Theory and Techniques, vol. 59, no. 6, pp. 1651-1657, April 2011
[21] MotoyukiSatoo, Jun Chen , TaskashiSekiguchi, ToyohiroChikyow, JiroYugami, Kazuto Ikeda, YuzuruOhji, “Pre-existing and process induced defect in high-k gate dielectrics ~ Direct observation with EBIC and impact on 1/f noise~," 2010 IEEE International Conference on IC Design and Technology (ICICDT), pp. 86-89 , June 2010
[22] Yu-Ting Chen, Kun-Ming Chen, “Effect of NH3 Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-k Dielectric nMOSFETs,” IEEE Trans. on Electron Devices, vol. 58, no. 3, pp. 812-818, January 2011
[23] L.F.Deng, P.T. Lai, “Effect of Different Annealing Gases on Pentacene OTFT With HfLaO Gate Dielectric,” IEEE Electron Device Letters, vol. 32, no. 1, pp. 93-95, November 2010
[24] L. K. J. Vandamme, Xiaosong Li, Dominique Rigaud, “ 1/f Noise in MOS Devices, Mobility or Number Fluctuations?,” IEEE Trans. on Electron Devices, vol. 41, no. 11, pp. 1936-1945, November 1994
[25] M. Nastasi, J.W. Mayer, “ Ion Implantation and Synthesis of Materials,” 2006 Springer
[26] David M. Pozar, “Microwave Engineering,” John Wiley & Sons
[27] G. Ghibaudo, T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectronics Reliability, vol. 42, pp. 573-582, 2002
[28] H. D. Xiong, “Characterization of electrically active defects in high-k gate dielectrics by using low frequency noise and charge pumping measurements,” Microelectronic Engineering, vol. 84, pp. 2230-2234, 2007