在下一代通訊5G系統中，超大型多輸入多輸出系統(large-scale MIMO system)被認為是候選技術。隨著下一代通訊系統中基地台所能制定的天線數目增加，超大型多輸入多輸出系統相對於傳統多輸入多輸出系統必須承受更高的運算複雜度。而為因應超大型多輸入多輸出系統所增加的運算複雜度，多種前編碼(precoding)技術相應而生。奇異值分解(singular value decomposition, SVD)是一種正交矩陣分解法，應用在無線通訊的前編碼矩陣設計上，可將超大型多輸入多輸出系統通道矩陣分解成互不影響的數個子通道。由於奇異質分解的效能會受到最弱的通道增益影響而衰減，因此通常選擇具較強空間增益的部分空間子通道進行傳輸。我們提出之奇異值分解演算法分為三階段，分別為基於Givens rotation之雙對角線化演算法、Golub-Reinsch SVD演算法輔以積極矩陣劃分和矩陣縮減機制與位移QR輔以提前終止機制演算法。
在硬體設計方面則根據Golub-Reinsch SVD演算法來設計硬體架構並透過C模擬硬體行為，預計支援維度為2×2~8×8複數矩陣。我們所提出之奇異值分解處理器擁有兩種工作模式，包含單一輸入矩陣奇異值分解和雙輸入矩陣平行奇異值分解。單一輸入矩陣奇異值分解支援維度為2×2~8×8之複數矩陣，雙輸入矩陣平行奇異值分解支援兩個維度為2×2~4×4之複數矩陣，並且此兩種模式皆支援非方陣之複數矩陣，如8×6、4×3等等。奇異值分解處理器採用以管線化(pipeline) coordinate rotation digital computer (CORDIC)為基礎的處理單元(processing element, PE)來完成奇異值分解。所提出的單一輸入8×8矩陣奇異值分解模式模擬時脈週期為445(clock cycles)，所提出的雙輸入4×4矩陣平行奇異值分解模式模擬時脈週期為118(clock cycles)。

In this thesis, we discuss the precoding schemes for multiple-input multiple-output (MIMO) systems. Singular value decomposition (SVD) plays an important role for MIMO precoding. To reduce the complexity of precoding based on SVD for large-scale MIMO systems, we first analyze the impact of SVD accuracy to the system performance and derive the error tolerance regarding the constellation, target bit error rate, and the number of transmitted spatial streams. Then, to perform SVD with given accuracy, aggressive split/deflation in the Golub-Reinsch (GR) SVD algorithm is adopted for finding the singular values. Furthermore, the shifted QR algorithm with the early termination mechanism is proposed to obtain only the desired singular vectors instead of all the singular vectors. Finally, we show that the aggressive split/deflation and early termination are effective, especially to process the correlated channel matrixes. The proper threshold setting can maintain the system performance with only tiny degradation. Compared to other SVD algorithms, the proposed scheme can achieve 15%~60% complexity reduction.
In hardware design, we design the architecture of SVD processor according to GR SVD algorithm. The SVD processor supports two modes: SVD for single matrix and parallel processing SVD for two matrices. The mode of SVD for single matrix can compute the SVD of 2×2~8×8 complex matrices. The mode of parallel processing SVD for two matrices can compute the SVD of 2×2~4×4 complex matrices. Furthermore, the two modes of SVD processor can compute the SVD of none-square complex matrices (e.g. 8×6, 4×3). In architecture design of SVD processor, we propose a pipelined CORDIC based processing element (PE) to implement GR SVD algorithm. 445 and 118 clock cycles for processing one 8×8 complex matrix and two 4×4 complex matrices.

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