本篇論文提出可適用於IEEE 802.16e標準的多碼率LDPC解碼器，目前LDPC解碼器在序列化的架構上，記憶體的使用率是很高的，在減少面積與硬體複雜度的前提下，記憶體所佔有的比重也會越來越大。同時為了使速度達到最佳化，用管線技術增加硬體使用率，記憶體必須具備同時讀寫的能力，因此採用雙埠記憶體的LDPC解碼器是普遍的。本篇論文特別針對此記憶體做優化與改良，採用單埠記憶體來取代雙埠記憶體，單埠記憶體比起雙埠記憶體在功率與面積上都佔有優勢，如何在相同記憶容量與不增加速度的前提下，將雙埠記憶體取代是本論文的重點。單埠的缺點在於不能同時間讀寫，因此在資料存取的排序上必須特別規劃，本論文針對IEEE 802.16e標準其六種檢查矩陣特別設計對應的資料排程以及資料在記憶體的位置，同時將記憶區塊拉出檢查節點與位元節點形成共用的第三區塊。經由FPGA驗證得知，單埠記憶體可完全取代雙埠記憶體以節省面積與功率，但在速度上會隨著檢查矩陣碼率的提高，而略劣於雙埠記憶體。由ISE軟體合成電路後可知本論文LDPC所提出之架構可以有最高112.94Mbps的生產量。

This thesis proposes a multi-code rate LDPC decoder in the application of IEEE 802.16e. The utilization rate of memory is very high when the LDPC decoder uses a serial architecture. To reduce the complexity of hardware, the percentage of memory unit is getting higher. In order to optimize the throughput rate, pipline technique can increase the hardware utilization. However, such architecture needs the memory to read and write at the same time. Hence the LDPC decoder usually uses two-port memory. This thesis focuses on the optimization and modification of memory design. We use single-port memory to replace two-port memory because single-port memory has the advantage of power consumption and area. The weakness of single-port memory is it cannot read and write at the same time. We should carefully arrange the data access schedule. In this thesis, we have designed the memory access schedules according to six parity check matrices for IEEE 802.16e. In the FPGA emulation results, single-port memory can completely replace the two port memory to save the chip area and power consumption. The throughput rate would be lower than two-port memory architecture as the code rate increases. Finally, the throughput rate of the proposed LDPC decoder can achieve 112.94 Mbps.

[1] C. Berrou, A. Glavieux, and P. Thitimagshima, “Near Shammon limit error-correcting coding and decoding: Turbo codes,” in Proc. Int. Conf. Communications(ICC’93), Geneva, Switzerland, pp.1064-1070,May 1993.
[2] R.G. Gallager, “Low-density parity-check codes”, IRE Trans. Inform. Theory, VolIT-8, pp.21-28, Jan 1962.
[3] D. J. C. Mackay and R.M. Neal, “Near Shannon limit performance of low density parity check codes”, IEE Electron. Lett., vol.32,no. 18pp. 1645-1646,Aug 1996
[4] Sae-Young Chung, G. David Forney Jr., Thomas J. Richardson and Rudiger Urbande, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Communications Letters, vol. 5, no. 2, pp. 58-60, Feb.2001
[5] IEEE 802.16e-2005, “IEEE Standard for Local and Metropolitan Area Network - Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems – Amendment 2: Physical and Medium Access Control layers for Combined Fixed and Mobile Operation in Licensed Bands,” 2005.
[6] F. R. Kschischang, B. J. Frey, and H.-A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. Inform Theory, vol. 47, pp.498-519, Feb. 2001.
[7] M. Fossorier, M. Mihaljevic, H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Trans. On Commun., vol. 47, no.5, pp. 673-680, May 1999.
[8] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inform. Theory, vol. 20, pp. 284-287, Mar. 1974.
[9] P. Roberston, E. Villebrun, and P. Hoeher, “A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain,” in Proc. IEEE Int. Conf. Communications, vol. 2, pp. 1009-1013, June 1995.
[10] J. Hagenauer, E. Offer, and L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Trans. Inform. Theory, vol. 42,pp. 429-445, Mar. 1996.
[11] X. Y. Hu, E. Eleftheriou, D. M. Arnold, and A. Dholakia., “Efficient implementations of the sum-product algorithm for decoding LDPC codes,” in Proc. IEEE GLOBECOM, San Antonio, TX, vol. 2, pp. 1036-1036E, 2001.
[12] E. Eleftheriou, T. Mittelholzer, and A. Dholakia, “Reduced-complexity decoding for low-density parity-check codes,” IEEE Electron. Lett., vol. 37, pp. 102-104, Jan. 2001.
[13] A. Anastasopoulos, “A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution,” in Proc. IEEE Globecom, San Antonio, TX, pp. 1021-1025, Nov. 2001.
[14] J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Comm., vol. 53, pp. 1288-1299, Aug. 2005.
[15] A. Blanksby and C. J. Howland, “A 220mW 1-Gbit/s 1024-Bit Rate-1/2 Low Density Parity Check Code Decoder,” in Proc. IEEE CICC, LasVegas, NV, USA, pp. 293-6, May 2001.
[16] A. Blankby and C. J. Howland, “A 690mW 1-Gbit/s 1024-b Rate-1/2 Low-Density Parity-Check code Decoder,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, March 2002.
[17] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 684-698, March 2006.
[18] Engling Yeo, Borivoje Nikolic, and Venkat Anantharam, “Architectures and Implementations of Low-Density Parity Check Decoding Algorithms,” Circuits and Systems, vol. 3, pp. III-437-III-440, Aug. 2002.
[19] M. M. Mansour and N. R. Shanbhag, “Low-Power VLSI Decoder Architecture for LDPC Codes,” Low Power Electronics and Design, 2002. ISLPED’02, pp. 284-289, 2002.
[20] M. M. Mansour and N. R. Shanbhag, “Turbo decoder architectures for low-density parity-check codes,” in Proc. IEEE GLOBECOM, Taipei, Taiwan, R.O.O., pp. 1383-1388, Nov. 2002.
[21] Brack T., Alles M., Kuenle F., and When N., “A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding,” Personal, Indoor and Mobile Radio Communications, 2006 IEEE 17th International Symposium on, pp. 1-5, Sept. 2006.