本論文之主題，在於研究探討自我對準矽化鎳奈米電極的製作，以取代高摻雜的複晶矽電極。希望藉此改善奈米電極的串聯阻抗，尤其是操作溫度低於室溫時，所衍生阻抗過大的問題。因此如何控制鎳與複晶矽奈米線的回火條件以形成矽化鎳，以及鎳在奈米線下橫向擴散的機制，則是我們研究的重點。
本論文利用不同大小的複晶矽奈米線，與鎳經回火後形成矽化鎳。藉由調變回火時間（0 ~ 270 sec），來控制奈米尺寸下矽化的長度（630 ~ 1900 nm）。所製作的自我對準矽化鎳奈米線，在調變不同奈米線的幾何尺寸，利用電性量測來進一步的了解，矽化鎳奈米線所形成電極之阻抗。

The theme of this paper is to study self-aligned nickel silicide nanoelectrodes to replace the highly doped poly-Si electrodes. Hope to improve the nano- electrodes series resistance, especially when the operating temperature is below room temperature, derived from the problem of excessive resistance. Therefore, how to control the mechanism of lateral diffusion at nano-scale when annealing Ni with poly-Si to from NiSi is our research.
In this thesis, we control the length ( 630 ~ 1900 nm ) of NiSi at nano-scale by modulating the annealing time ( 0 ~ 270 sec ) and making different sizes of poly-Si nano-wires to react with Ni while annealing NiSi. Making a self-aligned of electrode NiSi nano-wires and modulating different geometry of nano-wires can further the understanding of the electrode resistance that NiSi nano-wire forms by using the measurement.

[1] S. E. Thompson, M. Armstrong, C. Auth et al.,“A 90-nm logic technology featuring strained-silicon,”IEEE Trans. Electron Devices, vol. 51, no. 11, 2004.
[2] H. Iwai, T. Ohguro, and S. I. Ohmi,“NiSi salicide technology for scaled CMOS,”Microelectronic Engineering, vol. 60, pp. 157-169, 2002.
[3] 林鴻志，「奈米金氧化電晶體發展趨勢(II)」，NDL奈米通訊第七卷第二期，2000年。
[4] 莊達人，「VLSI製造技術」，第五章，2008年。
[5] K. Maex,“Silicides for integrated circuits：TiSi2 and CoSi2,”Material Science and Engineering, R11, 1993.
[6] J. P. Gambino, and E. G. Colgan,“Invited review silicides and ohmic contacts,”Materials Chemistry and Physics, vol. 52, pp. 99-146, 1998.
[7] T. Morimoto, T. Ohguro, H. S. Momose et al.,“Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI,”IEEE Trans. Electron Devices, vol. 42, no. 5, 1995.
[8] T. Ohguro, S. I. Nakamura, M. Koike et al.,“Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films,”IEEE Trans. Electron Devices, vol. 41, pp. 2305-2317, 1994.
[9] J. B. Lasky, J. S. Nakos, O. J. Cain, and P. J. Geiss,“Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2,”IEEE Trans. Electron Devices, vol. 38, pp. 262-269, 1991.
[10] H. M. Chuang, K. B. Thei, S. F. Tsai, C. T. Lu, X. D. Liao, K. M. Lee, and W. C. Liu,“Comparative study of double ion implant Ti-salicide and preamorphization implant Co-salicide for ultra-large-scale integration applications,”Semicond. Sci. Technol. vol. 17, pp. 1075-1080, 2002.
[11] Q. Xu, and C. Hu,“New Ti-salicide process using Sb and Ge preamorphization for sub-0.2 μm CMOS technology,”IEEE Trans. Electron Devices, vol. 45, pp. 2002-2009, 1998.
[12] G. T. Sarcona, M. Stewart, M. K. Hatalis, T. Aspect, and C. A. Sunnyvale, “Polysilicon thin-film transistors using self-aligned cobalt and nickel silicide source and drain contacts,”IEEE Electron Device Letters, vol. 20, no. 7, 1999.
[13] 劉傳璽，「半導體元件物理與製程-理論與實務」，第七章，2006年。
[14] W. M. Weber, L. Geelhaar, A. P. Graham et al.,“Silicon-nanowire transistors with intruded nickel-silicide contacts,”Nano Letters, vol. 6, no. 12, pp. 2660-2666, 2006.
[15] K. C. Lu, W. W. Wu, H. W. Wu, C. M. Tanner, J. P. Chang, L. J. Chen and K. N. Tu,“In situ control of atomic-scale Si layer with huge strain in the nanoheterostructure NiSi/Si/NiSi through point contact reaction,”Nano Letters, vol. 7, no. 8, pp. 2389-2394, 2007.
[16] B. Yu, X. H. Sun, G. A. Calebotta, G. R. Dholakia, and M. Meyyappan,“One-dimensional germanium nano-wires for future electronics,”Journal of Cluster Science, vol. 17, no. 4, 2006.
[17] R. Rao, N. DasGupta, and A. DasGupta,“Study of random dopant fluctuation effects in FD-SOI MOSFET using analytical threshold voltage model,”IEEE Transactions on Device and Materials Reliability, vol. 10, pp. 247-253, 2010.
[18] 顏瑋延，「自對準矽奈米線金氧半場效電晶體之研製」，國立中央大學，碩士論文，2006年。
[19] M. Qin, M. C. Poon, and C. Y. Yuen,“A study of nickel silicide film as a mechanical material,”Sensors and Actuators, vol. 87, pp. 90-95, 2000.
[20] M. Schmidt, T. Mollenhauer, T. Wahlbrink et al.,“Nickel-silicide process for ultra-thin-body SOI-MOSFETs,”Microelectronic Engineering, vol. 82, pp. 479-502, 2005.
[21] D. X. Xu, S. R. Das, C. J. Peters, and L. E. Erickson,“Material aspects of nickel silicide for ULSI applications,”Thin Solid Films, vol. 326, pp. 143-150, 1998.
[22] K. L. pey, P. S. Lee, and D. Mangelinck,“Ni (Pt) alloy silicidation on (100) Si and poly-silicon lines,”Thin Solid Films, pp. 137-145, 2004.
[23] T. Ohguro, M. Saito, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, and H. Iwai,“Thermal stability of CoSi2 film for CMOS salicide,”IEEE Trans. Electron Devices, vol. 47, pp. 2208-2213, 2000.
[24] 吳佳緯，「鍺奈米矽與矽奈米線電晶體之研製」，國立中央大學，碩士論文，2009年。