加速類比與數位混合訊號模擬的時間是現在單晶片系統設計設計驗證中很重要的一環，針對特定電路以硬體描述語言的方式對特定電路建立其行為模型，是一種有效率的混合訊號系統驗證方式，在本論文中我們希望能針對任意的電路發展一套自動建立行為模型方法，因為整個電路行為過於複雜，我們將設計的層級從電晶體層級拉到行為階層，透過將電路分割成小區塊，使其行為簡單化，並且使用迴歸分析的技巧將雜散的電路資訊公式化，以降低驗證流程的複雜度並且達到加速電路模擬的效果，由幾個電路上的實驗結果來看，我們確實能夠建構出對應的電路行為模型，並維持一定的準確度

Speeding up analog and mixed signal simulation is important in SoC design verification. Modeling circuit blocks by hardware description language for specific circuits and building their behavioral models is an efficient verification approach for AMS systems. In this thesis, we focus on the automatic generation of a behavioral model for arbitrary circuit netlist. By separating the circuit into several building blocks, the complexity of circuit behavior is reduced such that its behavioral model can be built by regression-based approach.
With those behavioral models, the verification complexity and the simulation time can be reduced significantly. As shown in the experimental results on several circuits, the proposed approach is able to generate the corresponding behavioral models automatically with good accuracy.

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