現今，由於晶片密度與操作頻率的增加，導致在IC設計中去考慮功率消耗變成是一個非常重要的問題。為了避免在IC設計過程中需要額外花費時間的重新設計流程，能在IC設計初期準確預估出所需功率消耗，是一件很重要的事。
預估序向電路與組合邏輯電路的功率消耗相比之下，序向電路被公認困難的多.原因是因為序向電路的功率通常在內部的狀態與輸入向量之間有一定程度上的時間關係。即使在傳統研究中，也很難描述出此類影響。基於這個理由，我們提出了一種方法，利用遞迴式類神經網路來建立序向電路的功率模型.此方法主要是去學習輸入ˋ輸出訊號間的統計數值與相對應的消耗功率。而遞迴式類神經網路具有內部的遞迴連結，我們希望透過此連結來降低訊號間的相依關係。
與傳統研究不同的是，我們的功率模型不但具有能自動調整功率分佈的非線性特徵與輸入序列間的相依關係，而且複雜度還相當的低。更重要的是，我們的類神經網路不需要低階的電路資訊，所以非常適合IP保護的特性。由實驗的結果可以看出即使在很短的輸入序列長度(50筆)，我們的功率模型也能提供相當不錯的準確度。換句話說，我們所提的模型能廣泛的使用在不同應用上。

Nowadays, the increasing in chip density and operating frequency have also made power dissipation a critical problem during IC design. In order to avoid costly redesign steps in IC design process, accurately estimate power dissipation on high-level of abstract is very important and necessary.
In sequential circuits, power estimation is considerably more difficult than combinational circuits, because the power dissipation also depend on internal states and strong temporal correlations often exist in the input sequences, which are also hard to handle their effects in traditional approaches. For this reason, we propose a novel power model for CMOS sequential circuits by using recurrent neural networks (RNNs) to learn the relationship between input/output signal statistics and the corresponding power dissipation, because the RNNs has the internal feedback to handle temporal correlations.
Unlike traditional approach of power estimation (for example: building lookup table), not only our neural power model automatically consider the non-linear characteristic of power distributions and the temporal correlation of the input sequences but also has very low complexity.
More importantly, using our neural power model for power estimation does not require any transistor-level or gate-level description of the circuits. So it is suitable for IP protection. The experiment results have shown that the estimations are still accurate even for short sequence with only 50 pattern-pairs. It shows that our power model can be used in various applications.

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