隨著製程的演進，晶片的尺寸也逐年下降，製程變異以及電路佈局(Layout)所產生的寄生效應對於晶片的影響也越來越顯著，然而在傳統類比電路設計自動化流程中並沒有很仔細地考慮寄生效應的影響，因為這會耗費相當多的模擬時間。
本篇論文提出一套考慮電路佈局所產生之寄生效應的類比積體電路自動化設計流程。使用佈局樣板預估出寄生電阻電容值後，將預估之數值加入電壓驅動設計方法，並使用非線性規畫去找出最佳解。加入寄生效應之自動化設計流程可以在佈局前預估佈局後之電路效能，進一步降低佈局前及佈局後電路效能的差異，並且可以避免佈局後電路效能不符合訂定規格又須重新設計的情況發生，大大降低設計時間。跟之前有考慮寄生效應的相關研究相比，我們的研究可以大幅降低所需的計算時間，並且可避免過分設計電路。整套流程以MATLAB實現，而在非線性規劃(nonlinear programming)的部分用MATLAB的 Optimization tool box來找尋最佳解，而在自動產生電路佈局上則是以C/C++及Tcl/Tk 程式語言實現，自動化佈局的過程能在Laker環境下執行。從實驗數據的觀察可知，本論文所提出的方法可以在非常短的時間內達到設計出符合使用者所給定規格之電路，並在佈局後電路效能皆有達到訂定規格的標準。

In deep submicron process, process variation and parasitic effects make a great impact on chip performance. However, the parasitic effects are often not well considered in traditional circuit sizing flow due to the long simulation time with complex parasitic devices. This thesis proposes an automatic design flow for analog circuits, which considers the parasitic effects during synthesis. Considering the possible parasitic resistance and capacitance in the given layout template, a bias-driven optimization approach based on nonlinear programming is proposed to generate an optimal design. The parasitic-aware sizing flow successfully reduces the performance shift after layout and prevents the possible redesign loops. Compared with the traditional simulation-based approaches, the proposed equation-based approach can achieve the required specifications with less computation and less overdesign. The proposed sizing algorithm has been implemented with the optimization tool box in MATLAB, incorporating with an automatic layout generation tool implemented with C/C++, Tcl/Tk and Laker. As demonstrated on several cases, the proposed approach is indeed an effective and efficient solution to achieve the required specification after layout.

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