擺置階段評估繞線完成度的有效率區域壅塞模型

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研究生：	龐立遠 Li-Yuan Pang
論文名稱：	擺置階段評估繞線完成度的有效率區域壅塞模型 An Efficient Local-Congestion Model for Routability Estimation in Placement
指導教授：	劉建男 Chien-Nan Liu 陳泰蓁 Tai-Chen Chen
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2015
畢業學年度：	103
語文別：	中文
論文頁數：	38
中文關鍵詞：	區域壅塞
外文關鍵詞：	Local Congestion
相關次數：	點閱：16 下載：0
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隨著超大型積體電路的快速演進，電路的可繞度（Routability）問題愈趨嚴重。一般在繞線階段時才能準確得知電路可繞度之資訊，然而若此時才發現電路的可繞度不足，在設計上會浪費大量的時間重新進行擺置與再繞線。因此若在擺置階段就考慮電路的可繞度資訊並能及時發現問題，即可避免時間的浪費。
為了精準的預估可繞度，本篇論文採用全域繞線研究做為基底，但目前絕大部分的全域繞線研究皆沒有考慮細部繞線階段可能產生的壅塞問題，這導致即使完成了全域繞線，仍有相當大的機率無法得到無壅塞（Congestion-free）的細部繞線結果。因此，本篇論文提出了適用於擺置階段的快速區域壅塞模型（Local congestion model），搭配適合在擺置階段使用的快速全域繞線器，能夠提早預知區域壅塞的情形，並且提早迴避壅塞區域（Congested region），或者識別不可繞（Unroutable）的電路。實驗結果顯示，本篇論文所提出的方法可以在短時間內預估電路的區域壅塞，使得全域繞線器可以提早得知細部繞線階段之可繞度資訊。

With the advances of Very-Large-Scale Integration circuits, the routability problem has become more and more significant. Conventionally, circuit routability can only be evaluated precisely after routing stage. However, if the routability is not sufficient, it will waste lots of time to re-place and re-route. Thus, routability evaluating in placement stage is important to discover potential routing problems and avoid redesign efforts.
For accurate routability evaluation, this thesis proposes a method based on global routing. However, most of the global routing researches didn’t consider the possible congestions occurred in the detailed routing stage. It is possible that congestion-free detailed routing results are still not available. Therefore, a fast local congestion model for placement stage is proposed in this thesis. Combined with a fast global router, the proposed fast local congestion model can predict the distribution of routing congestion to avoid congested regions and identify unroutable circuits. Experimental results showed that the proposed model can obtain local congestion information fast in placement stage and help the global router to evaluate the routability of the circuits.

摘要    iii
Abstract    iv
致謝    v
目錄    vi
圖目錄    ix
表目錄    xi
第一章、緒論    1
1-1 超大型積體電路的成長與遭遇的困難    1
1-2 擺置階段    2
1-3 繞線階段    3
1-4 研究動機    4
1-5 論文架構    5
第二章、背景知識    6
2-1 繞線背景知識    6
2-1-1 連線（Net）    6
2-1-2 全域繞線階段（Global Routing Stage）    6
2-1-3 細部繞線階段（Detailed Routing Stage）    7
2-2 區域壅塞（Local Congestion）    8
2-2-1 障礙物（Blockage）    8
2-2-2 區域連線（Local Net）    8
2-3 繞線架構介紹與解釋    9
2-3-1 並行繞線（Concurrent Routing）與循序繞線（Sequential Routing）    9
2-3-2 交涉式繞線（Negotiation-based Routing）    10
2-3-3 拔除與再繞線（Rip-up and Reroute）    10
2-4 繞線方法介紹與解釋    10
2-4-1 樣式繞線（Pattern Routing）    10
2-4-2 單調繞線（Monotonic Routing）與單向單調繞線（Unilateral Monotonic Routing）    11
2-4-3 繞線框（Routing Box）設置    12
2-5 相關研究    12
2-5-1 快速之全域繞線相關研究    13
2-5-2 考量區域壅塞之相關研究    14
2-5-3 全域繞線與細部繞線整合之相關研究    17
2-6 問題定義    18
第三章、擺置階段評估繞線完成度的有效率區域壅塞模型    19
3-1 準備階段    19
3-1-1 拆分多端點連線    20
3-1-2 紀錄障礙物    20
3-1-3 二維投影    21
3-2 區域壅塞估計階段    21
3-2-1 分解全域繞線格    21
3-2-2 紀錄障礙物資訊    22
3-2-3 區域連線繞線    23
3-2-4 結果萃取    23
3-3 選擇全域繞線器    25
3-3-1 NCTU-GR 2.0 [5]    25
3-3-2 本篇之全域繞線器    27
第四章、實驗結果與討論    29
4-1 工作平台與實驗說明    29
4-2 數據與討論    29
4-2-1 驗證區域壅塞模型之有效性    29
4-2-2 驗證區域壅塞模型之效率    32
4-2-3 使用NCTU-GR 2.0 [5]繞線    33
第五章、結論與未來展望    36
參考文獻    37

                                

[1] Gate count of Intel CPU available at http://zh.wikipedia.org/wiki/%E8%8B%B1%E7%89%B9%E5%B0%94%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8%E5%88%97%E8%A1%A8
[2] Gate count of Intel CPU available at http://ark.intel.com/
[3] Z. Cao, T. Jing, J. Xiong, Y. Hu, L. He, and X. Hong, "DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm," Proc. Asia and South Pacific Design Automation Conf., pp.256-261, Jan. 2007.
[4] W. H. Liu, Y. L. Li, and C. K. Koh, "A Fast Maze-Free Routing Congestion Estimator With Hybrid Unilateral Monotonic Routing," Proc. Intl. Conf. on Computer-Aided Design, pp.713-719, Nov. 2012.
[5] W.-H. Liu, W.-C. Kao, Y.-L. Li, and K.-Y. Chao, "NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing," IEEE Trans. on Computer-Aided Design and Integrated Circuits and Systems, pp.709-722, May 2013.
[6] Y. Wei, C. Sze, N. Viswanathan, Z. Li, C. J. Alpert, L. Reddy, A. D. Huber, G. E. Tellez, D. Keller, and S. S. Sapatnekar, "GLARE: Global and Local Wiring Aware Routability Evaluation," Proc. ACM/IEEE Design Automation Conf., pp.768-773, Jun. 2012.
[7] M. K. Hsu, Y. F. Chen, C. C. Huang, S. Chou, T. H. Lin, T. C. Chen, and Y. W. Chang, “NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs,” IEEE Trans. on Computer-Aided Design and Integrated Circuits and Systems, pp. 1914-1927, Dec. 2014
[8] M. Cho and D. Z. Pan, "BoxRouter: a new global router based on box expansion and progressive ILP," Proc. ACM/IEEE Design Automation Conf., pp.373-378, Jul. 2006.
[9] Y. Xu , Y. Zhang, and C. Chu , "FastRoute 4.0: Global Router with Efficient Via Minimization," Proc. Asia and South Pacific Design Automation Conf., pp.576-581, Jan. 2009.
[10] Y. Zhang and C. Chu, "RegularRoute: An efficient detailed router with regular routing patterns," Proc. ACM/SIGDA Intl. Symp. on Physical Design, pp.146-151, Mar. 2011.
[11] Y. Zhang and C. Chu, "GDRouter: Interleaved global routing and detailed routing for ultimate routability," Proc. ACM/IEEE Design Automation Conf., pp.597-602, Jun. 2012.
[12] M. Pan, C. Chu “FastRoute: A Step to Integrate Global Routing into Placement,” Proc. Intl. Conf. on Computer-Aided Design, pp.464-471, Nov, 2006.
[13] Chu, C.; Yiu-Chung Wong, “FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design,” IEEE Trans. on Computer-Aided Design and Integrated Circuits and Systems, pp.70-83, Jan, 2008
[14] 賈立瑋, “考量快速且精確局部壅塞模型之全域繞線,” 國立中央大學電機工程研究所碩士論文, July 2014
[15] Available at http://www.ispd.cc/contests/11/ispd2011_contest.html
[16] Available at http://www.ispd.cc/contests/15/ispd2015_contest.html

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