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研究生： 徐銘言
Ming-yan Hsu
論文名稱： DVB-T基頻接收機之FPGA設計與實現
Design and FPGA Implementation of Baseband Receiver for DVB-T System
指導教授： 陳逸民
Yih-Min Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
畢業學年度： 100
語文別： 中文
論文頁數： 80
中文關鍵詞： 里徳所羅門碼 、快速傅立葉轉換器 、數位電視廣播
外文關鍵詞： Reed-Solomon code, Fast Fourier Transform Processor, DVB-T
相關次數： 點閱：15  下載：0 
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    • DVB-T(Digital Video Broadcasting - Terrestrial)是歐洲廣播聯盟(European
    Broadcast Union，EBU)所制定的數位電視廣播規格，也是目前我國所採用的數位電視廣播系統。
    在本論文中，我們採用目前我國數位電視廣播之規格，設計並且實現DVB-T即時基頻接收機在FPGA實驗板上，此接收機之數位訊號處理模組中，包括了數位降頻器、訊號同步器、快速傅立葉轉換處理器、通道估測器、通道等化器、軟式決策器、訊號解交錯器及通道解碼器。系統架構以Matlab模擬分析後，在效能與硬體複雜度上選取適當之參數及規格後再以硬體實現。首先以Verilog硬體描述語言撰寫，經由ModelSim軟體邏輯驗證及模擬時序後，再以FPGA板做測試及驗證其功能與效能。

    DVB-T, which is a Digital Video Broadcasting standard ratifies by European Broadcast Union and an abbreviation for Digital Video Broadcasting-Terrestrial, is the digital video broadcasting standard adopted in Taiwan. In this thesis, we discuss the design and implementation issues of a real-time baseband receiver for DVB-T system with FPGA. The digital signal processing units required for the baseband receiver include digital down converter, signal synchronizer, Fast Fourier Transform processor, channel estimator/equalizer, symbol deinterleaver, soft decision logics, bit deinterleaver, Viterbi decoder and Reed-Solomon decoder.
    The algorithm and specification for each digital signal processing unit is first designed with a compromise between the performance and the hardware complexity. Then the hardware is programmed using Verilog hardware description language and logically verified with ModelSim. Finally, the real-time hardware is implemented and verified with FPGA.

    摘 要 v ABSTRACT vi 致謝 vii 目錄 viii 圖目錄 xi 表目錄 xv 第一章 緒論 1 1-1 研究動機與背景 1 1-2 章節提要 2 第二章 數位電視地面廣播系統簡介 3 2-1 正交分頻多工系統簡介 3 2-1-1 OFDM 調變原理 3 2-1-2 CP-OFDM簡介 6 2-2 DVB-T系統簡介與規格 8 2-2-1 參考訊號之傳輸模式 8 2-2-2 DVB-T系統規格與參數 9 第三章 數位電視地面廣播接收端硬體架構 18 3-1 數位降頻器 18 3-1-1 數位降頻器之基本原理 18 3-1-2 座標軸數位旋轉計算器 19 3-1-3 數位濾波器 21 3-2 時序同步器 23 3-2-1 延遲相關器 23 3-2-2 峰值檢測器 25 3-2-3 載波頻率同步器 26 3-2-4 符碼同步器 28 3-3 快速傅立葉轉換器 29 3-3-1 碟型運算器架構 31 3-3-2 旋轉因子產生單元 33 3-3-3 位元反轉排序 34 3-3-4 碼框同步器 35 3-4 通道估測/等化器 36 3-4-1 通道估測器 36 3-4-2 通道等化器 38 3-5 解交錯器 40 3-5-1 符碼解交錯器 40 3-5-2 位元解交錯器 43 3-6 軟式決策器 44 3-7 腓特比解碼器 50 3-8 封包同步器 51 3-9 外解交錯器 52 3-10 里徳所羅門解碼器 53 第四章 硬體設計與實現 58 4-1 系統設計流程 58 4-2 定點數模擬 59 4-2-1 CORDIC微旋轉次數 59 4-2-2 FFT規格模擬 62 4-2-3 通道估測/等化規格模擬 68 4-2-4 軟式決策規格 69 4-3 系統模擬 71 4-4 電路合成報告 76 4-5 模擬環境與平台 77 第五章 結論與未來展望 78 參考文獻 79

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