本論文提出一個操作在5 GHz之低相位雜訊全數位次諧波注入鎖定式鎖相迴路。藉由一個額外之延遲鎖定迴路產生10個相位可用於次諧波注入之相位，此次諧波注入式鎖相迴路可以用較低的參考時脈但同時達到與高參考時脈之次諧波注入式鎖相迴路之低相位雜訊效果，同時利用一偽亂波產生器選擇注入相位，將注入之時序打亂，破壞其週期性，可以有效降低次諧波注入式鎖相迴路之高參考突波問題，透過選擇不同組合的注入相位順序，本架構提供了多種注入鎖定模式，可依照對需求之輸出訊號規格調整，達到不同的相位雜訊壓制量與參考突波量，同時由於使用了全數位式的架構，與傳統類比式鎖相迴路比較，其面積與功率消耗較少。
本論文之全數位式鎖相迴路使用90 nm CMOS製程實現晶片，其操作頻率為5 GHz，並且可在100 MHz參考頻率下擁有近於於1 GHz之次諧波注入鎖定之相位雜訊壓制效果，相位雜訊約為-99 dB。電路在操作電壓為1 V時，功率消耗為6.0 mW，而使用亂波注入的機制對於參考突波的衰減量約為14 dB。整體晶片面積為830 × 830 um2，核心電路的面積為228 × 161 um2。

In this thesis, a 5 GHz low phase noise all-digital sub-harmonically injection-locked phase-locked loop (ADSILPLL) is proposed. An all-digital delay-locked loop (ADDLL) is added to provide extra 10 phases of low-phase-noise reference clock for the sub-harmonically injection operation. Proposed PLL uses the different sequence combination of those phases to achieve good phase noise performance without using high reference frequency. By adopting a pseudo chaotic code generator, the injected phase sequences can be randomized and break the periodicity of injection signal to solve the high reference spur issue at SILPLLs. By changing the injected phase sequence, this PLL also provides several different mode with different phase noise performance and reference spur performance for different specification requirement.
The experiment chip of the proposed ADPLL was implemented with 90 nm CMOS process. The measured output frequency is 5 GHz at 1.0 V supply voltage and power consumption is 6.0 mW. The phase noise is equal to -99 dB at 1 MHz frequency offset with 100 MHz reference frequency. The reference spur suppression is about 14 dB compared to full-speed injection. The full chip area is 830 × 830 um2 and the core area is 228 × 161 um2 .

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