本論文主要著重應用於微波及毫米波的次諧波注入壓控振盪器及其運用在鎖頻迴路與應用於類比數位轉換器前端的高速追蹤與保持放大器。第二章及第三章分別闡述了次諧波注入鎖定鎖頻迴路的分析、模擬及量測結果，第四章為CMOS寬頻追蹤與保持放大器的設計與分析。
第二章介紹次諧波注入鎖定鎖頻迴路的理論模型架構，並且提出各個方塊元件的理論模型轉移函數，根據推導出來的模型架構去設計整個次諧波注入鎖定鎖頻迴路，並且用理論計算值的結果去驗證整個系統的穩定性。在製程、電壓及溫度變異下，這次所提出的次諧波注入鎖定鎖頻迴路具有高穩定性，所設計次諧波注入鎖定鎖頻迴路使用的製程是台積電提供的90 nm通用互補式金氧半場效電晶體製程。量測結果完整呈現次諧波注入鎖定振盪器、次諧波注入鎖定鎖頻迴路以及鎖相迴路。在頻率為10.4 GHz時，鎖頻迴路具有-130.38 dBc/Hz的相位雜訊，而最低的抖動量為30.3 fs，此時頻率為10.3 GHz，而電路的直流功率消耗為26 mW。
第四章為追蹤與保持放大器的設計及分析，在輸入級緩衝器方面，運用了分佈式放大器的結構來使整個追蹤與保持放大器的頻寬提升，而追蹤與保持開關的部分採用了一個額外的P型MOS來解決電荷注入效應對無失真動態範圍的影響，而輸出緩衝級採用了疊接放大器的架構，用來提升追蹤與保持放大器整體的線性度。本次設計的追蹤與保持放大器所使用的製程是台積電提供的90 nm低功耗互補式金氧半場效電晶體製程。量測的結果具有0~17 GHz的3 dB增益頻寬，而無失真動態範圍在12 GS/s以及6 GS/s分別為-42.1 dB及 -41.9 dB，直流功率消耗為216 mW。

This thesis focuses on the sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) for microwave and millimeter-wave applications and the high speed track-and-hold amplifier (THA) for front-end of analog-to-digital converter (ADC). The analysis, simulation and measurement of the SILVCO with FLL are presented in Chapter 2 and 3, respectively. The design and analysis of a broadband CMOS THA are proposed in Chapter 4.
The theoretical model of SILVCO with FLL are proposed in Chapter 2. The transfer functions of the other blocks in SILVCO with FLL are presented. The SILVCO with FLL is designed using the proposed model, and the calculated results are presented to verify the loop stability. The proposed SILVCO with FLL demonstrates good robustness versus process, voltage, and temperature variations. The proposed SILVCO with FLL is fabricated using TSMC 90 nm CMOS general purpose (GP) process. The measurements of the SILVCO with FLL and phase-locked loop (PLL) are completely presented. As the output frequency is 10.4 GHz, the proposed SILVCO with FLL features a phase noise of -130.38 dBc/Hz and the minimum jitter features 30.25 fs when output frequency is 10.3 GHz. The dc power consumption of the proposed SILVCO with FLL is 26 mW.
The design and analysis of the proposed THA are presented in Chapter 4. The distributed amplifier (DA) is adopted to enhance the bandwidth of the proposed THA. The dummy switch topology is also adopted in the track-and-hold stage to avoid the charge injection. The cascode amplifier is used to enhance the linearity of the proposed THA. The proposed THA is fabricated using TSMC 90 nm CMOS low power (LP) CMOS process. The proposed THA features a 3-dB bandwidth from 0 to 17 GHz. The measured spurious-free dynamic ranges (SFDR) of the proposed THA are -42.1 dB and -41.9 when the sampling rates are 12 GS/s and 6 GS/s, respectively. The dc power consumption of the proposed THA is 216 mW.

[1] T. Quemerais, D. Gloria, D. Golanski, and S. Bouvot, “High-Q MOS Varactors for Millimeter-Wave Applications in CMOS 28-nm FDSOI” IEEE Electron Device Letters, vol. 36, no. 2, pp. 87-89, Feb. 2015.
[2] S. Elabd, S. Balasubramanian, Q. Wu, T. Quach, A. Mattamana, and W. Khalil, “Analytical and Experimental Study of Wide Tuning Range mm-Wave CMOS LC-VCOs” IEEE Trans. Circuits Syst. Regul. Pap., vol. 61, no. 5, pp. 1343-1354, May 2014.
[3] Y. W. Chen, T. N. Luo, H. Cruz, and Y. J. E. Chen, “A W-band harmonically enhanced CMOS divide-by-3 frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 4, pp. 257–259, Apr. 2014.
[4] W. Dangwei, W. Lihua, and L. Fangyao, “Steady-state Tracking Error Analysis of GPS Receiver Frequency Locked Loop” in 2013 Fourth International Conference on Intelligent Control and Information Processing (ICICIP) Beijing, pp. 114-118, 2013.
[5] W. Khalil, S. Shashidharan, T. Copani, S. Chakraborty, S. Kiaei, and B. Bakkaloglu, “A 700-μA 405-MHz all-digital fractional-N frequencylocked loop for ISM band applications,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1319–1326, May 2011.
[6] C.-C. Li, T.-P. Wang, C.-C. Kuo, M.-C. Chuang, and H. Wang, “A 21 GHz complementary transformer coupled CMOS VCO,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 4, pp. 278–280, Apr. 2008.
[7] A. Visweswaran, R. B. Staszewski, and J. R. Long, “A low phase noise oscillator principled on transformer-coupled hard limiting,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 300–311, Feb. 2014.
[8] P. Andreani, X. Wang, L. Vandi, and A. Fard, “A study of phase noise in Colpitts and LC-tank CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1107–1118, May 2005.
[9] K.-K. Huang, and D. D. Wentzloff, “A 60 GHz Antenna-Referenced Frequency-Locked Loop in 0.13 μm CMOS for Wireless Sensor Networks” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2956–2965, Dec. 2011.
[10] H. Matsumoto, and K. Watanabe, “Switched-capacitor frequency-tovoltage and voltage-to-frequency converters based on charge-balancing principle,” in Proc. Int. Symp. Circuits Syst., Jun. 1988, vol. 3, pp. 2221–2224.
[11] C. E. Lin, and A. S. Hou, “Design of frequency-to-voltage converter using successive-approximation technique,” in Proc. Instrum. Meas. Technol. Conf., 2003, vol. 2, pp. 1438–1443.
[12] H. T. Bui et al., “Design of a high-speed differential frequency-tovoltage converter and its application in a 5 GHz frequency locked loop,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 4, pp. 766–774, Apr. 2008.
[13] A. Djemouai, M. Sawan, and M. Slamani, "New 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach," in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 1999), vol. 2, Orlando, USA, May 1999, pp. 89-92.
[14] D. Borio, L. Camoriano, L. Lo Presti, M. Fantino, "DTFT-Based Frequency Lock Loop for GNSS Applications," IEEE Transaction on Aerospace and Electronic Systems, vol 44, No 2, April 2008.
[15] 高曜煌，射頻鎖相迴路IC設計，第二章，滄海書局，民國 94 年。
[16] 劉深淵、楊清淵，鎖相迴路，第一章、第二章，滄海書局，民國 100 年。
[17] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.
[18] Y.-A. Li, M.-H. Hung, S.-J. Huang, and J. Lee, “A fully integrated 77GHz FMCW radar system in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp. 216-217.
[19] T. Mitomo, N. Ono, H. Hoshino, Y. Yoshihara, O. Watanabe, and I. Seto, “A 77 GHz 90 nm CMOS transceiver for FMCW radar applications,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 928–937, Apr. 2010.
[20] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1606-1617, Jul. 2011.
[21] R. Appleby, and R. N. Anderton, “Millimeter-wave and submillimeter-wave imaging for security and surveillance,” IEEE Proc., vol. 95, no. 8, pp. 1683-1690, Aug. 2007.
[22] P. Chen, P. Peng, C. Kao, Y. Chen, and J. Lee, “A 94GHz 3D Image Radar Engine with 4TX/4RX Beamforming Scan Technique in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2013, pp. 146-147.
[23] C.-A. Lin, J.-L. Kuo, K.-Y. Lin, and H. Wang, “A 24 GHz low power VCO with transformer feedback,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2009, pp. 75–78.
[24] A. Pottbacker, U. Langmann, and H.-U. Schreiber, “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747–1751, Dec. 1992.
[25] Y.-H. Peng, and L.-H. Lu, “A 16-GHz triple-modulus phase-switching prescaler and its application to a 15-GHz frequency synthesizer in 0.18-m CMOS,” IEEE Trans. Microw. Theory Tech., vol.55, no.1, pp.44-51, Jan. 2007.
[26] R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, Nov. 2004.
[27] Y.-H. Peng, and L.-H. Lu, “A Ku-band frequency synthesizer in 0.18-μm CMOS technology,” IEEE Microw.Wireless Compon. Lett., vol. 17, no. 4, pp. 256-258, Apr. 2007.
[28] H. Zhuo, Y. Li, W. Rhee, and Z. Wang, “A 1.5GHz All-Digital Frequency-Locked Loop with 1-bit ΔΣ Frequency Detection in 0.18μm CMOS,” in Proc. Int. Symp. VLSI DAT, Taiwan, May 2014.
[29] C. F. Liang and K.J. Hsiao, “An injection-locked ring PLL with self-aligned injection window,” in IEEE Int. Solid-State Circuits Conf., Tech. Dig., Feb. 2011., pp. 90-92.
[30] B. M. Helal, C.-M. Hsu, K. Johnson, and M. H. Perrott, “A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning Loop,” IEEE J. Solid-State Circuits, vol. 44, pp. 1391-1400, May 2009.
[31] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 56, no. 2, pp. 117–121, Feb. 2009.
[32] H.-Y. Chang, Y.-L. Yeh, Y.-C. Liu, M.-H. Li, and K. Chen, “A low jitter low phase noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65 nm CMOS technology,” IEEE Trans. Microwave Theory & Tech., vol. 62, no. 03, pp. 543-555, Mar. 2014.
[33] Y.-L Yeh, C.-H. Lu, M.-H. Li, H.-Y. Chang, and K. Chen, “A 2.2-2.4 GHz Self-aligned Sub-harmonically Injection-locked Phase-locked Loop using 65 nm CMOS Process,” in Proc. Eur. Micro. Integr. Circuits Conf., Oct. 2014, pp. 269-272.
[34] J. Lee, and H. Wang, "Study of subharmonically injection-locked PLLs," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009.
[35] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-µm CMOS Technology for High Speed MilimeterWave Wireless Systems,” IEEE ICCSC 2008, pp. 812-815.
[36] N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, A. Nazemi, U. Singh, and A. Momtaz, “An 8.5-11.5-Gbps SONET transceiver with referenceless frequency acquisition,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1875–1884, Aug. 2013.
[37] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
[38] J. Lee, A. Leven, J.S. Weiner, Y. Baeyens, Y. Yang, W.-J. Sung, J. Frackoviak, R.F. Kopf, and Y.-K. Chen, “A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology,” IEEE J. Solid-State Circuits, vol. 38, no. 06, pp. 1533-1539, June 2003.
[39] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 1-GSample/s, 15-GHz input bandwidth master–slave track-and-hold amplifier in InP DHBT technology,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3181-3187, Dec. 2009.
[40] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 40 G samples/s InP-DHBT Track-and-Hold Amplifier with high dynamic range and large bandwidth,” in 2012 8th Int. Symp. On Commun. Syst., Networks & Digital Signal Process., July 2012, pp. 1-4.
[41] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, M. Riet, J. Godin, and G. Pailler, “A 50-GHz-small-signal-bandwidth 50 GSa/s Track&Hold amplifier in InP DHBT technology,” in 2012 IEEE MTT-S Int. Microw. Symp. Dig., June 2012, pp. 1-22.
[42] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, and J. Godin, “A 4 GSa/s, 16-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT technology,” in 2012 20th Telecommun. Forum, Nov. 2012, pp. 502-505.
[43] J.Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, J. Godin, G. Pailler, “70 GSa/s and 51 GHz bandwidth track-and-hold amplifier in InP DHBT process,” Electronics Lett., vol.49, pp. 388-389, Mar. 2013.
[44] S. Shahramian, A. C. Carusone, and S. P. Voinigescu, “Design methodology for a 40-GSamples/s track and hold amplifier in 0.18-μm SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 41, pp. 2233-2240, Sept. 2006.
[45] X. Li, W.-M. Kuo, Y. Lu, R. Krithivasan, J.D. Cressler, and A.J. Joseph, “A 5-bit, 18 GS/sec SiGe HBT track-and hold amplifier,” in 2005 IEEE Compound Semiconductor Integr. Circuit Symp., Oct. 2005, pp. 105-108.
[46] X. Li, W.-M. L. Kuo, and J. D. Creeler, “A 40 GS/s SiGe track-and-hold amplifier,” in IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008, Oct. 2008, pp. 1-4.
[47] S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, vol. 44, pp. 1709-1720, June 2009.
[48] M. Buck, M. Grözing, M. Berroth, M. Epp, and S. Chartier, “A 6 GHz input bandwidth 2 Vpp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS,” in 2013 IEEE RFIC Symp. Dig., June 2013, pp. 159-162.
[49] H. Orser, and A. Gopinath, “A 20 GS/s 1.2 V 0.13μm CMOS switched cascode track-and-hold amplifier,” IEEE Trans. Circuits Syst. II, Ex Briefs, vol 57, pp. 512-516, July 2010.
[50] H.-L. Chen, S.-C. Cheng, B.-W. Chen, “A 5-GS/s 46-dBc SFDR track and hold amplifier,” in 2012 Int. Symp. on Intelligent Signal Processing and Communications Systems (ISPACS), 4-7 Nov. 2012, pp. 636-639.
[51] G. Tretter, D. Fritsche, C. Carta, F. Ellinger, “10-GS/s track and hold circuit in 28 nm CMOS,” in 2013 Int. Semiconductor Conf. Dresden-Grenoble (ISCDG), Sept. 2013, pp. 1-3.
[52] J. Proesel, G. Keskin, J.-O. Plouchart, L. Pileggi, "An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection," 2010 IEEE Custom Integrated Circuits Conf., Sept. 2010, pp. 1-4.
[53] Y.-C. Liu, H.-Y. Chang, and K. Chen, “A 12 GB/s 3-GHz input bandwidth track-and-hold amplifier in 65 nm CMOS with 48-dB spur-free dynamic range,” in 2014 IEEE MTT-S Int. Microw. Symp. Dig., Florida, USA, Jun. 2014.
[54] H.-Y. Chang, Y.-C. Liu, S.-H. Weng, C.-H. Lin, Y.-L. Yeh, and Y.-C. Wang, “Design and analysis of a DC–43.5-GHz fully integrated distributed amplifier using GaAs HEMT–HBT cascode gain stage,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 2, pp. 443-455, Feb. 2011.
[55] H.-Y. Chang, C.-H. Lin, Y.-C. Liu, Y.-L. Yeh, K. Chen, and S.-H. Wu, “65 nm CMOS dual-gate device for Ka-band broadband low noise amplifier and high-accuracy quadrature voltage controlled oscillator,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 06, pp. 2402-2413, Jun. 2013.