| 研究生: |
郭哲均 che-chun kuo |
|---|---|
| 論文名稱: |
覆晶技術應用於毫米波積體電路 |
| 指導教授: |
詹益仁
yi-jen chan |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 通訊工程學系 Department of Communication Engineering |
| 畢業學年度: | 93 |
| 語文別: | 中文 |
| 論文頁數: | 116 |
| 中文關鍵詞: | 共平面波導濾波器 、毫米波積體電路 、覆晶封裝 |
| 外文關鍵詞: | CPW filters, MMIC, FlipChip |
| 相關次數: | 點閱:11 下載:0 |
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本論文成功利用覆晶式封裝技術(Flip Chip)成功研發出覆晶式微波積體電路( Flip Chip Microwave Integrated Circuit),所設計的電路中有20GHz 放大器 13.2GHz 振盪器,其放大器模擬約在20GHz有14dB的增益,量測增益為10dB,其振盪器模擬的頻譜在13.2GHz有10dBm的振盪功率,其量測大約漂到10GHz有0dBm的振盪功率。
本論文又提供了30GHz全新縮小型低通濾波器(1.49mm x 1.6mm),大大改善歩階式阻抗低通濾波器(Step Impedance)耗費大量面積(2.35mm x 1.6mm),並且有更好的電路特性其縮小型S21於40GHz為-31dB傳統歩階式S21於40GHz為-22dB。
在30GHz帶通濾波器我們提供了一個較為窄頻5GHz頻寬的,以及一個基本型和其對照ACPS(Asymmetric Coplanar Striplines),縮小面積佈局的帶通濾波器
我們還研發主動電路的實現,利用CPW設計28GHz低雜訊放大器31GHz功率放大器,其增益模擬18dB於28GHz NF2.4dB,實際量測 16dB於26GHz NF3dB
CPW設計的功率放大器其模擬增益18dB於31GHz,Pae於1dB 23%,Pout 20dBm,實際量測增益15dB於31GHz,Pout19dBm,Pae於1dB 20%
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[16] 何建廷, ” 氧化鋁基板上微波功率放大器之研製,” 碩士論文, 國立中央大學, 2000
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[18] 蘇碩彬,”異質接面雙極性電晶體之大訊號模型建立及其在功率放大器之應用,”碩士論文,國立中央大學, 2002
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Microwave Theory and Techniques, IEEE Transactions on , Volume: 49 , Nov 2001
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