交換電容式三角積分D類放大器電路設計｜國立中央大學博碩士論文系統

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研究生：	陳俊方 Jiun-fang Chen
論文名稱：	交換電容式三角積分D類放大器電路設計 Design of a Switched-Capacitor Sigma-Delta Class-D Amplifier
指導教授：	蘇純賢 Chun-Hsien Su 蔡佩芸 Pei-Yun Tsai
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	97
語文別：	中文
論文頁數：	85
中文關鍵詞：	三角積分調變器、D類放大器
外文關鍵詞：	Class-D Amplifier, Sigma-Delta Modulator
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D類放大器以其高效率及低功耗的優點，已被廣泛地應用於音訊產品上面。然而，傳統利用脈衝調變技術的D類放大器在三角波轉換成脈波訊號的過程中常伴有線性度的問題，造成D類放大器還原出來的音訊訊號品質較差。為改善此一問題，本論文採用用於高解析度的類比和數位資料轉換器電路上面的三角積分調變技術來設計D類放大器電路。此類三角積分調變D類放大器可避以免非線性的問題，且其利用雜訊移頻技巧可以抑制頻寬內的雜訊，提升效能。
針對D類放大器的電路設計，本論文將探討輸出級所包含的類比非理想的成份，包含訊號調變效應、輸出級後的波形失真、與輸出級供應電壓源的雜訊等等對系統效能造成的影響。本論文所設計的三角積分調變D類放大器電路,包含一個四階的三角積分調變器，超取樣率為64，工作頻率為2.56MHz。為降低D類放大器非理想效應對電路的影響，此電路採用閉迴路機制，以全差動交換電容式電路架構設計來實現。電路方面則是透過TSMC 0.18um製程來實現。系統在工作頻率2.56M、供應電壓3.3V、最大功耗1W及負載為4ohms的條件下，模擬結果可知，採閉迴路機制的D類放大器較開迴路機制而言，更能夠有效的改善訊雜比20dB。

Class D audio amplifiers have been widely used in audio applications for their high efficiency and less power dissipation. However, traditional pulse width modulation (PWM)-based class D amplifiers suffer from the linearity problems when converting pulse signals, causing poor quality for reconstructed output waveform. In this thesis, the class-D audio amplifier is designed with the sigma-delta modulation techniques used in high resolution data converters and is called as sigma-delta class-D amplifiers. By performing oversampling and noise shaping, the sigma-delta class-D amplifier can avoid the non-linearity problem and suppress the in-band noise
To fulfill the class-D amplifier circuit design, this thesis analyzes the influences of analog non-idealities at the output stage, including modulation errors, nonlinear errors in timing and shape of the output waveform, and the noise on power supplies. The designed class-D amplifier is with a closed-loop, forth-order sigma-delta modulator, an oversampling ratio of 64, and an operating frequency of 2.56MHz. The circuit is implemented with fully differential switch-capacitor circuitry and is with TSMC 0.18um process. Simulation results show that the closed-loop class D amplifier (with the operating frequency: 2.56MHz、supply voltage: 3.3V、power dissipation: 1W and load: 4ohms) can be improved 20dB SNR compared to the open-loop circuit.

摘要 .............................................................................................Ⅰ
英文摘要 ...................................................................................... Ⅱ
目錄 ............................................................................................ Ⅲ
圖目錄...........................................................................................Ⅵ
表目錄............................................................ ...............................X
第一章 介紹
1-1 動機....................................................................................1
1-2 論文組織..............................................................................3
第二章 三角積分調變器原理................................................................4
2-1尼奎斯特資料轉換器................................................................4
2-2 量化....................................................................................6
2-3 超取樣技術..........................................................................10
2-4 低階三角積分調變器..............................................................11
2-4-1 一階三角積分調變器.....................................................11
2-4-2 二階三角積分調變器.....................................................16
2-5 高階三角積分調變器..............................................................17
2-5-1 單迴路式架構..............................................................18
2-5-2 串疊式架構.................................................................19
2-6 總結...................................................................................21
第三章 D類放大器...........................................................................22
3-1 D類放大器的架構…...............................................................23
3-2 D類放大器的效率…...............................................................24
3-3 半橋式與全橋式架構..............................................................25
3-4 濾波器電路..........................................................................26
3-5 D類放大器的非理想效應.........................................................28
3-6 論文架構.............................................................................29
3-7 總結…….............................................................................30
第四章 高階單迴路三角積分器設計與模擬.............................................31
4-1 行為模擬…….......................................................................31
4-2 非理想模型….. .....................................................................36
4-2-1 開關熱雜訊.................................................................36
4-2-2 時脈抖動….................................................................38
4-2-3 運算放大器雜訊...........................................................39
4-2-4 運算放大器有限增益.....................................................40
4-2-5 運算放大器有限頻寬及迴轉率.........................................42
4-3 非理想模型模擬....................................................................43
4-4 總結…................................................................................45
第五章 電路設計與模擬.....................................................................46
5-1 交換式電容積分器.................................................................46
5-2 電路規格的評估與設計...........................................................48
5-2-1 電容評估....................................................................48
5-2-2 開關評估....................................................................49
5-3 運算轉導放大器評估…...........................................................55
5-3-1 直流增益....................................................................55
5-3-2 迴轉率與單位增益頻寬..................................................57
5-4 運算放大器….......................................................................59
5-5 時脈產生電路.......................................................................67
5-6 比較器電路….......................................................................68
5-7 加法器電路….......................................................................72
5-8 調變器模擬結果與比較...........................................................73
5-9 輸出級電路….......................................................................77
5-10 D類放大器開迴路與閉迴路模擬結果與比較................................78
第六章 結論....................................................................................81
參考文獻..................................................................................83

                                

[1] C. L. Simon and V. L. Chia-Chang " A High Efficiency 0.5W BTL Class D Audio Amplifier with RWDM Technique " Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific,27-30 Jan. 2004 Page(s):535-536.
[2] D. A. Johns and K. Martin, " Analog Integrated Circuit Design ", John Wiley & Sons, New York, 1997.
[3] S. Haykin, " Communication System",3rd ed. John Wiley & Sons, New York, 1994.
[4] R. Schreier, and G. C. Temes " Understanding Delta-Sigma Data Converters ", IEEE Press, John Wiley &Sons, Inc., 2005.
[5] R. Schreier, "An empirical study of high-order single-bit delta-sigma modulators", IEEE Trans. Circuits and Syst. II, vol. CAS-40, no. 8, pp. 461-466, Aug. 1993.
[6] R. Baird and T. Fiez, "Stability analysis of high-order delta-sigma modulator for ADC’s," IEEE Trans. Circuits and Syst. II, vol. CAS-41, no. 1, pp. 59-62, Jan. 1994.
[7] J. Candy and G. Temes, "Oversampling Delta-Sigma Data Converters:Theory, Design, and Simulation’ ", IEEE Press, New York, NY, 1992.
[8] S. R. Norsworthy, R. Schreier and G. C. Temes, "Delta-Sigma Data Converters: Theory, Design, and Simulation," IEEE Press, New York, 1997.
[9] E. Gaalaas,.; B.Y.,Liu; N. Nishimura,.; R. Adams; K. Sweetland,.; "Integrated stereo Delta-Sigma class D amplifier," IEEE J. Solid-State Circuits, vol. 41, pp. 2382-2389, Nov. 2006.
[10] Y. Fujimoto, P. L. Re, and M Miyamoto, "A Delta-Sigma Modulator for a 1-Bit Digital Switching Amplifier, " IEEE J. Solid-state Circuits, vol. 40, no. 9, pp. 1865-1871, Sept. 2005.
[11] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto,F. Maloberti, "Modeling sigma-delta modulator non-idealities in SIMULINK", Proceedings of ISCAS ''99, Vol. 2, pp. 384-387, 1999.
[12] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, F. Cusinato, A. Baschirotto, "Behavioral modeling of switched-capacitor sigma-delta modulators", IEEE Trans. on Circuits and Systems I, Vol. 50, No. 3, pp. 352-364, 2003.
[13] G. C. Teams, " Finite amplifier gain and bandwidth effects in switch-capacitor filters " IEEE Journal Solid-State Circuits, vol SC-15,pp. 358-361,June.1980.
[14] B. E. Boser and B. A. Wooley, "The Design of Sigma-Delta Modulation Analog-to-Digital Converters, " IEEE Journal of Solid-State Circuits, vol. SC-23,pp.1298-1308,Dec 1988.
[15] A. Leuciuc and C. Mitrea, " On the Effect of OP-Amp Gain in Delta Sigma Modulators, " IEEE , ISCAS, 2000.
[16] P. E. Allen and D. R. Holberg, " CMOS Analog Circuit Design", 2nd Edition,
Oxford University Press, Inc., 2002.
[17] B. Y. Kamath, R. G. Meyer and P. R. Gray, "Relationship Between Frequency
Response and Settling Time of Operational Amplifiers," IEEE J. Solid-state
Circuits, vol. sc-9, no. 6, pp. 347-352, Dec. 1974.
[18] B. Razavi, "Design of Analog CMOS Integrated Circuits" McGraw-Hill, Inc., 2001.
[19] A. M. Marques, V. Peluso, Michel S. J. Steyaert, Willy Sansen, " A 15-bit Resolution 2-MHz Nyquist Rate Sigma-Delta ADC in a 1-um CMOS Technology "IEEE Journal of Solid-State Circuits, Vol 33, No. 7, July 1998.
[20] A. Feldman, " High-Speed, Low-Power Sigma-Delta Modulators for RF Baseband Applications, " Ph.D. dissertation, University of California at Berkeley (ERL Memo #UCB/ERL M97/62), 1997.
[21] J. W. Lee and et al.A 2W BTL single -chip class-D power amplifier with very high efficiency for audio applications. ISCAS 2000.

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