適應性決策回授等化器(ADFE)從效能與硬體複雜度考量皆優於線性等化器，因此被廣泛的使用於通信傳輸系統中，用來消除通道所造成之符號間彼此干擾現象。然而，因為適應性決策回授等化器在係數修正與資料等化處理上皆有回授路徑，會影響到實際所能處理的資料速度，導致適應性決策回授等化器在高速應用上受到一定的限制。理論上，要打破回授的限制必須要在回授路徑上做前瞻運算，接著利用平行化來達到增加速度的目的。傳統上會採用資料前瞻的做法，然而資料前瞻必須先將所有可能結果算出，導致硬體複雜度隨著平行化與等化器係數長度而快速增加。
有別於傳統作法，本論文於二元脈衝振幅調變系統中之接收端等化器提出係數前瞻法，也就是利用算出回授等化器的前瞻係數而達到打斷回授路徑的目的。此外，配合該係數前瞻演算法，我們也提出自我前瞻濾波器架構以降低整體運算複雜度。該架構除了在訊雜比 (SNR)上具有與傳統非平行適應性決策回授等化器有相近的表現之外，面積上還具有比其他已知的平行適應性決策回授等化器擁有小非常多的優點。在係數修正方面，我們提出一套降速修正的演算法(Batch Mode Coefficients Update, BMCU)，該演算法可以兼顧追蹤通道變化以及達到高速等化資料的需求。此外，為了避免雜訊被前饋濾波器 (FFF) 放大，本論文提出前饋濾波器雜訊抑制型適應性決策回授等化器的架構 (FNS-ADFE)。模擬結果顯示，相比於傳統ADFE，FNS-ADFE可提升2 dB 訊雜比或降低錯誤率到百分之一。
實作上是採用40 nm CMOS-GP製程。該測試晶片的面積為275 μm × 275 μm (或約等效於28.5 k 個邏輯閘)。平均功率消耗在低供應電壓低資料率時（0.75V, 10 Gbps）為 2.3 pJ/bit、在正常供應電壓中資料率時（0.9V, 13 Gbps）為3.5 pJ/bit、而在高供應電壓高資料率時（1.1V, 16 Gbps）為 5.8 pJ/bit。

Adaptive Decision Feedback Equalizers (ADFEs) are widely used to reduce the inter-symbol interferences (ISIs) caused by channels in communication systems since ADFEs are better than Adaptive Linear Equalizers (ALEs) in both signal-to-noise ratio (SNR) and hardware complexity points of views. However, the data rate of an ADFE is limited due to the feedback path in both the coefficients update part and the data equalization part. In theorem, to do lookahead and then parallel can eliminate the limitation of data rate and the data lookahead scheme is usually used. Data lookahead scheme requires calculating all-possible results; hence the hardware complexity grows quickly with the parallelism and the tap-number of the ADFE.
In this dissertation, we propose the coefficients-lookahead scheme for the ADFEs in the receivers of 2-level Pulse Amplitude Modulation (2-PAM) systems, that is, to find out the coefficients for lookahead scheme. Based on the coefficients-lookahead scheme, the self-lookahead filter and the high speed architecture are proposed. The proposed architecture has almost the same SNR with conventional ADFE and has hardware complexity growing slowly with parallelism. In coefficients adaption, we propose a slow updating method, Batch Mode Coefficients Update (BMCU) algorithm to fit the requirement for channel tracking and high data rate. Besides, to avoid noise enhancement at the feed-forward filter (FFF), a FFF noise-suppression ADFE (FNS-ADFE) architecture is proposed which has 2 dB better SNR or 1% less bit error rate than that of a conventional ADFE.
The test-chip has been fabricated in a 40nm CMOS-GP technology with the core size as 275 μm × 275 μm (or 28.5k equivalent gates count), and dissipates 2.3 pJ/ bit at 10 Gbps with low-supply voltage (0.75 V), 3.5 pJ/bit at 13 Gbps with normal-supply voltage (0.9 V) and 5.8 pJ/bit at 16 Gbps with high-supply voltage (1.2 V).

[1] D. A. George, R. R. Bowen, and J. R. Storey, “An Adaptive Decision Feedback Equalizer,” IEEE Trans. Commun. Technol., vol. 19, no. 3, pp. 281-293, Jun. 1971.
[2] C. A. Bel_ore and J. John H. Park, “Decision Feedback Equalizer,” IEEE Trans. Commun. Technol., vol. 67, no. 8, pp. 1143-1156, Aug. 1979.
[3] W. S. Kim, C. K. Seong, and W. Y. Choi, “A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms,” IEEE Trans. Circuits Syst. II, vol. 59, no. 9, pp. 553-557, Sept. 2012.
[4] A. Momtaz and M. M. Green, “An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 629-639, Mar. 2010.
[5] M. S. Chen, Y. N. Shih, C. L. Lin, H. W. Hung, and J. Lee, “A 40Gb/s TX and RX Chip Set in 65nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2011, pp. 146-148.
[6] J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, “A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.
[7] M. Ramezani, M. Abdalla, A. Shoval, M. V. Ierssel, A. Rezayee, A. McLaren, C. Holdenried, J. Pham, E. So, D. Cassan, and S. Sadr, “An 8.4mW/Gb/s 4-lane 48Gb/s Multi-Standard-Compliant Transceiver in 40nm Digital CMOS Technology,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2011, pp. 352-354.
[8] G. Balamurugan, J. Kennedy, G. Banerjee, J. E. Jaussi, M. Mansuri, F. OMahony, B. Casper, and R. Mooney, “A Scalable 515 Gbps, 1475 mW Low-Power I/O Transceiver in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1010-1019, Apr. 2008.
[9] M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins, P. Hunt, A. Joy, P. Khandelwal, B. Killips, T. Krause, S. Lytollis, A. Pickering, M. Saxton, D. Sebastio, G. Swanson, A. Szczepanek, T. Ward, J. Williams, R. Williams, and T. Willwerth, “A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2007, pp. 436-591.
[10] J. Cao, B. Zhang, U. Singh, D. Cui, A. Vasani, A. Garg, W. Zhang, N. Kocaman, D. Pi, B. Raghavan, H. Pan, I. Fujimori, and A. Momtaz, “A 500mW Digitally Cali-brated AFE in 65nm CMOS for 10Gb/s Serial Links over Backplane and Multimode Fiber,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2009, pp. 370-371,371a.
[11] B. Abiri, A. Sheikholeslami, H. Tamura, and M. Kibune, “An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3140-3149, Dec. 2011.
[12] E. H. Chen, R. Yousry, and C. K. K. Yang, “Power Optimized ADC-Based Serial Link Receiver,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 938-951, Apr. 2012.
[13] B. Abiri, A. Sheikholeslami, H. Tamura, and M. Kibune, “A 5Gb/s Adaptive DFE for 2x Blind ADC-Based CDR in 65nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, Feb. 2011, pp. 436-438.
[14] K. K. Parhi, VLSI Digital Signal Processing Systems : Design and Implementation. New York, USA: John Wiley, LTD., 1999.
[15] M. Renfors and Y. Neuvo, “The Maximum Sampling Rate of Digital Filters under Hardware Speed Constraints,” IEEE Trans. Circuits Syst. II, vol. 28, pp. 196-202, Mar. 1981.
[16] A. Gatherer and T. H. Y. Meng, “High Sampling Rate Adaptive Decision Feedback Equalizers,” in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), vol. 2, Apr. 1990, pp. 909-912.
[17] A. Gatherer and T. H. Y. Meng, “A Robust Adaptive Parallel DFE Using Extended LMS,” IEEE Trans. Signal Process., vol. 41, no. 2, pp. 1000-1005, Feb. 1993.
[18] K. J. Raghunath and K. K. Parhi, “Parallel Adaptive Decision Feedback Equalizers,” IEEE Trans. Signal Process., vol. 41, no. 5, pp. 1956-1961, May 1993.
[19] N. R. Shanbhag and K. K. Parhi, “Pipelined Adaptive DFE Architectures Using Relaxed Look-Ahead,” IEEE Trans. Signal Process., vol. 43, no. 6, pp. 1368-1385, Jun. 1995.
[20] K. K. Parhi, “Pipelining of Parallel Multiplexer Loops and Decision Feedback Equalizers,” in IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP), vol. 5, May 2004, pp. 17-21.
[21] K. K. Parhi, “Design of Multigigabit Multiplexer-Loop-Based Decision Feedback Equalizers,” IEEE Trans. VLSI Syst., vol. 13, no. 4, pp. 489-493, Apr. 2005.
[22] D. Oh and K. K. Parhi, “Low Complexity Design of High Speed Parallel Decision Feedback Equalizers,” in IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Sep. 2006, pp. 118-124.
[23] C. H. Lin, A. Y.Wu, and F. M. Li, “High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems,” IEEE Trans. Circuits Syst. II, vol. 53, pp. 911-915, Sep. 2006.
[24] “http://www.usb.org/press/USB-IF Press Releases/SuperSpeed 10Gbps USBIF Final.pdf.”
[25] J. Barry, E. Lee, and D. Messerschmitt, “Capacity Penalty Due to Ideal Zero-Forcing Decision-Feedback Equalization,” IEEE Trans. Inf. Theory, vol. 42, no. 4, pp. 1062-1071, Jul. 1996.
[26] J. Cio_, G. Dudevoir, M. Vedat Eyuboglu, and J. Forney, G.D., “MMSE Decision-Feedback Equalizers and Coding. I. Equalization Results,” IEEE Trans. Commun., vol. 43, no. 10, pp. 2582-2594, Oct. 1995.
123
[27] W.-R. Wu and Y.-M. Tsuie, “An LMS-based Decision Feedback Equalizer for IS-136 Receivers,” IEEE Transactions on Vehicular Technology, vol. 51, no. 1, pp. 130-143, Jan. 2002.
[28] G. Long, F. Ling, and J. G. Proakis, “The LMS Algorithm with Delayed Coefficient Adaptation,” IEEE Trans. Acoust., Speech, Signal Process., vol. 37, no. 9, pp. 1397-1405, Sep. 1989.
[29] B. E. Jun, D. J. Park, and Y. W. Kim, “Convergence Analysis of Sign-Sign LMS Algorithm for Adaptive Filters with Correlated Gaussian Data,” in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)., vol. 2, May 1995, pp. 1380-1383.
[30] D. Chao and D. Wang, “Iteration Bounds of Single-Rate Data Flow Graphs for Concurrent Processing,” IEEE Trans. Circuits Syst. I, vol. 40, no. 9, pp. 629-634, Sep. 1993.
[31] D. Chan and L. Rabiner, “Analysis of Quantization Errors in the Direct Form for Finite Impulse Response Digital Filters,” IEEE Trans. Audio Electroacoust., vol. 21, no. 4, pp. 354-366, Aug. 1973.
[32] H. Tuan, T. Son, P. Apkarian, and T. Nguyen, “Low-Order IIR Filter Bank Design,” IEEE Trans. Circuits Syst. I, vol. 52, no. 8, pp. 1673-1683, Aug. 2005.
[33] J. Ma, K. K. Parhi, and E. F. Deprettere, “Pipelined CORDIC-Based Cascade Orthogonal IIR Digital Filters,” IEEE Trans. Circuits Syst. II, vol. 47, no. 11, pp. 1238-1253, Nov. 2000.
[34] J. W. Cooley, P. A. W. Lewis, and P. D. Welch, “The Fast Fourier Transform and Its Applications,” IEEE Trans. Educ., vol. 12, no. 1, pp. 27-34, Mar. 1969.
[35] Roberts and R. A., Digital Signal Processing. Boston, USA: Addison-Wesley, 1987.
[36] S. Haykin, Adaptive Filter Theory, 4th Edition. New Jersey, USA: Prentice Hall, Inc., 2002.
[37] D. Zhao, F. Huang, X. Tang, and X. Sun, “Design of VGA for 6 GHz Radio Frequency Communication System,” in IEEE MTT-S International Microwave Workshop Series on Millimeter Wave Wireless Technology and Applications (IMWS), Sep. 2012, pp. 1-4.
[38] E. Eweda, “Transient Performance Degradation of The LMS, RLS, Sign, Signed Regressor, and Sign-Sign Algorithms with Data Correlation,” IEEE Trans. Circuits Syst. II, vol. 46, no. 8, pp. 1055-1062, Aug. 1999.
[39] V. Rajaraman and H. Wertz, “On Stability and Steepest Descent,” IEEE Transactions on Automatic Control, vol. 8, no. 1, pp. 61-62, Jan. 1963.
[40] T. Chen, Y. Zakharov, and C. Liu, “Low-Complexity Channel-Estimate Based Adaptive Linear Equalizer,” IEEE Signal Process. Lett., vol. 18, no. 7, pp. 427-430, Jul. 2011.
[41] M. Rupp and A. Bahai, “Training and Tracking of Adaptive DFE Algorithms under IS-136,” in IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), Apr. 1997, pp. 341 -344.
[42] R. Zukunft, S. Haar, and T. Magesacher, “A Blind Adaptation Algorithm for Decision Feedback Equalization for Dual-Mode CAP-QAM Reception,” in IEEE Global Telecommunications Conference (GLOBECOM), vol. 1, Nov. 2002, pp. 307-311.
[43] W. Chung and C. You, “Fast Recovery Blind Equalization for Time-Varying Channels Using Run-And-Go Approach,” IEEE Trans. Broadcast., vol. 53, no. 3, pp. 693-696, Sept. 2007.
[44] R. Merched, “Fast Computation of Constrained Decision Feedback Equalizers,” IEEE Trans. Signal Process., vol. 55, no. 6, pp. 2446-2457, Jun. 2007.
[45] S. Kasturia and J. M. Cio_, “Vector Coding with Decision Feedback Equalization for Partial Response Channels,” in IEEE Global Telecommunications Conference (GLOBECOM), Nov. 1988, pp. 853-857.
[46] Y. C. Lin, S. J. Jou, and M. T. Shiue, “High Throughput Concurrent Lookahead Adaptive Decision Feedback Equalizer,” IET Circuits, Devices Syst., vol. 6, pp. 52-62, 2012.
[47] Y. C. Lin, S. J. Jou, and M. T. Shiue, “High Throughput Extended Incremental Coefficient-Lookahead Filters Based Adaptive Decision Feedback Equalizer,” International Journal of Electrical Engineering, vol. 19, no. 3, pp. 115-126, 2012.
[48] “10GBASE-LX4, IEEE Std 802.3ae-2002,” http://www.ieee802.org/3/ae.
[49] N. A. Dhahir and J. M. Cio_, “Fast Computation of Channel-Estimate Based Equalizers in Packet Data Transmission,” IEEE Trans. Signal Process., vol. 43, no. 11, pp.2462-2473, Nov. 1995.
[50] J. S. Baek, S. W. Park, and J. S. Seo, “Fast Start-Up Decision Feedback Equalizer Based on Channel Estimation for 8VSB DTV System,” IEEE Trans. Broadcast., vol. 53, no. 1, pp. 38-47, Mar. 2007.
[51] D. L. Duttweiler, J. E. Mazo, and D. G. Messerschmitt, “An Upper Bound on the Error Probability in Decision-Feedback Equalization,” IEEE Trans. Inf. Theory, vol. 20, pp. 490-497, Jul. 1974.
[52] A. Levine and R. McGhee, “Cumulative Distribution Functions for A Sinusoid Plus Gaussian Noise (Corresp.),” IEEE Trans. Inf. Theory, vol. 5, no. 2, pp. 90-91, Jun. 1959.
[53] J. Newell, “High Speed Pseudo-Random Binary Sequence Generation for Testing and Data Scrambling in Gigabit Optical Transmission Systems,” in IEE Colloquium on Gigabit Logic Circuits, Apr. 1992, pp. 1-4.