類比數位轉換器與數位類比轉換器的功用在超大型積體電路的設計內佔十分重要的地位。這兩種元件使得其他邏輯運算元件能與真實世界接軌，更使超大型積體電路能融入一般人的生活並為大眾服務。然而，類比數位轉換器與數位類比轉換器內含的電容卻會因為製程階段的不匹配效應，使得這兩個元件無法正確運作。
為了修正不匹配效應，我們以新的電容擺置方法決定類比數位轉換器與數位類比轉換器內電容的擺置方式。同時，提出一個精準的誤差模型用以評估類比數位轉換器與數位類比轉換器內電容經過製程後所承受的不匹配效應。透過使用新的方法與誤差模型，實驗結果顯示，與最新研究所提出的方法相比，本論文提出的方法可以提升13%的匹配性。

The usage of analog-to-digital converters (ADC) and digital-to-analog converters (DAC) is very important in many VLSI designs. These two devices connect other logic-related devices to the real world and turn into the technologies we are using today. However, during fabrication process, the capacitors in ADCs and DACs suffer from mismatch induced error which may stop the ADCs and DACs from functioning properly.
To solve the problem, we proposed a new capacitor array placement method to determine how the capacitors in ADCs and DACs should be placed. An accurate mismatch model is also proposed to estimate the mismatch induced error among the capacitors before ADCs and DACs are fabricated. With the new method and mismatch model, the experimental result showed that 13% increasing in matchability compared with the state-of-the-art method.

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