隨著互補式金氧半場效電晶體電子元件尺寸縮小，現今矽材料將面臨到微縮下的物理極限，III-V族半導體搭配高介電係數氧化物儼然成為未來發展趨勢，但首要克服的挑戰是氧化層與半導體界面的高缺陷密度問題。
本論文針對氧化鉿與砷化銦之電容結構製備與介面缺陷處理作探討。我們除了透過串聯腔體超高真空系統中傳輸建構一臨場原子層沉積系統，以降低砷化銦表面氧化的機會外，也利用電容-電壓量測與光電子能譜儀探討了數種表面結構以及三甲基鋁處理對於電容的影響。經過此臨場系統與表面處理，大幅降低了氧化鉿/砷化銦介面的原生氧化層，包含氧化銦與氧化砷，成功地在約1.5 奈米的等效氧化層厚度下、VFB±1V維持4.1×10-9 A/cm2低漏電流特性，利用電導法(Conductance method)在室溫下可得到低介面缺陷密度, Dit=3.6×1012 1/eVcm2。

The scaling of Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is approaching to the physical limitations when scaling down. One potential solution is to replace the traditional SiO2/Si MOS structure with high-k oxide/III-V semiconductors. In this work, the HfO2/InAs as our MOS structure and focus on reducing the interface trap density methods.
In order to avoid the native oxide on the semiconductor surface, the in-situ atomic layer deposition systems was set up. Effects of surface structures and surface treatment on interfacial and electrical properties were investigated. XPS revealed a conspicuously reduction of indium oxide and no detection of arsenic oxide in the interface by these approaches. Reduced density of interface defects by removing the In2O3、In2O and As-As traps was observed. By these approaches, the low Dit of 3.6×1012 1/eVcm2 at room temperature determined by conductance method with low leakage current density of 4.1×10-9 /cm2 at VFB±1V have been achieved.

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