軟性電子(flexible electronics)具有許多優點，常應用於可攜式產品。由於可撓式薄膜電晶體許多特性與傳統CMOS 不同，CMOS 設計技術不能直接應用於軟性電子產品上，而且激烈的參數變化和產品老化效應會對軟性電子電路的設計形成巨大的挑戰，尤其是敏感的類比電路，因此一套可提升軟性電子可靠度的電路設計方法是必不可少的。
本論文提出了一種針對可撓式薄膜電晶體的類比電路自動化最佳化技術，來解決軟性電子中激烈的參數變化和電路老化效應的問題。為了提高精準度與電路設計流程的效率，本論文將最壞情況距離(worst case distance)的概念導入以方程式為基礎的自動化設計流程中，可撓式薄膜電晶體的特殊性質，例如激烈的參數變動敏感、彎曲效應、臨界電壓漂移現象等等，都有考慮在最佳化流程之中，可有效提高良率。此外，本論文提出了一種在電路設計流程當中快速預估電路老化後參數的近似方式，可以有效地考慮電路效能漂移現象。實驗結果顯示，本論文提出的自動化設計方式，可以考量電路可靠度的問題，有效地提高設計良率和產品的壽命，解決了軟性電子類比電路設計的問題。

Flexible electronics are possible alternative to conventional silicon electronics
for portable consumer applications with many advantages. Due to quite different
properties of flexible TFTs, conventional CMOS design techniques cannot be used
directly on flexible electronics. The severe parameter variations and aging effects of
flexible electronics are big challenges for circuit designers, especially for sensitive
analog circuits. Robust circuit design methodology is essential to implement more
complex applications with flexible electronics.
This thesis proposes an automatic robust optimization technique for analog
circuits with flexible TFTs to deal with the severe parameter variations and aging
effects. To improve both accuracy and efficiency of the circuit sizing procedure, the
WCD concept is integrated into equation-based sizing approach in this work to
optimize the design yield with accurate variation consideration. The different
properties of flexible TFTs such as bending and severe Vt variation are considered in
the optimization algorithm. Furthermore, this thesis proposes a fast approximation
technique to predict the parameter aging in the circuits to consider the shifted
performance in the circuit sizing procedure. As demonstrated on different cases with
flexible electronics, the proposed robust optimization technique can significantly
improve the fresh design yield and the lifetime yield, which solves the main difficulty
of designing the analog circuits with flexible electronics.

[1] E. Cantatore, T. C. T. Geuns, G. H. Gelinck, E. Veenendaal, A. F. A. Gruijthuijsen, L. Schrijnemakers, S. Drews, D. M. Leeuw, ‘‘A 13.56-MHz RFID System Based on Organic Transponders,’’ Journal of Solid-State Circuits,　vol. 42, no. 1, pp. 84-92, 2007.
[2] M. Takamiyal, T. Sekitanil, Y. Miyamotol, Y. Noguchi, H. Kawaguchi, T. Someyal, T. Sakurai, ‘‘Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches,’’ International Solid-State Circuits Conference, pp. 362-609, 2007.
[3] T. Sekitani, S. Iba, Y. Kato, Y. Noguchi, T. Someya, T. Sakurai, “Ultraflexible organic field-effect transistors embedded at a neutral strain position,” Applied Physics Letters, vol.87, no.17, pp.173502-173502-3, 2005.
[4] H. Gleskova, S. Wagner, W. Soboyejo, and Z. Suo, “Electrical Response of Amorphous Silicon Thin-Film Transistors under Mechanical Strain,” Journal of Applied Physics, vol. 92, no.10, pp. 6224-6229, 2002.
[5] W. S. Wong, S. Sambandan, T. N. Ng, M. L. Chabinyc, “Materials, Processing, and Testing of Flexible Image Sensor Arrays,” Design & Test of Computers, vol. 28, no. 6, pp. 16-23, 2011.
[6] R. Blache, J. Krumm, W. Fix, “Organic CMOS Circuits for RFID Applications,” International Solid-State Circuits Conference, pp. 208-209, 2009.
[7] T.-C. Huang, J.-L. Huang, K.-T. Cheng, “Robust Circuit Design for Flexible Electronics,” Design & Test of Computers, vol. 28, pp. 8-15, 2011.
[8] U. Sobe, K.-H. Rooch, A. Ripp, and M. Pronath, “Robust analog design for automotive applications by design centering with safe operating areas,” Transactions on Semiconductor Manufacturing, vol. 22, no. 2, pp. 217-224, 2009.
[9] R. Shringarpure, S. Venugopal, Z. Li, L. T. Clark, D. R. Allee, E. Bawolek, D. Toy, “Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175℃,” Transactions on Electron Devices, vol.54, no. 7, 2007.
[10] T.-C. Huang, K.-T. Cheng, “Design for Low Power and Reliable Flexible Electronics: Self-Tunable Cell-Library Design,” Journal Display Technology, vol. 5, no. 6, pp. 206-215, 2009.
[11] H. Marien, M. Steyaert, N. Aerle, P. Heremans, “An Analog Organic First-Order CT △Σ ADC on a Flexible Plastic Substrate with 26.5db Precision,” International Solid-State Circuits Conference, pp. 136-137, 2010.
[12] S.-H. Chen, K.-C. Chu, J.-Y. Lin, C.-H. Tsai, “DFM/DFY Practices During Physical Designs for Timing,” Asia and South Pacific Design Automation Conference, pp. 232-237, 2007.
[13] M. Buhler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath, A. Ripp, “DFM/DFY Design for Manufacturability and Yield - Influence Of Process Variations in Digital, Analog and Mixed-Signal Circuit Design,” Design Automation and Test in Europe, pp. 1-6, 2006.
[14] X. Li, J. Wang, L. T. Pileggi, T.-S. Chen, W. Chiang, “Performance-Centering Optimization for System-Level Analog Design Exploration,” International Conference on Computer-Aided Design, pp. 422-429, 2005.
[15] H. E. Graeb, “Analog Design Centering and Sizing,” Springer, 2007.
[16] X. Pan, H. Graeb, “Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations,” Advances in Analog Circuits, 2011.
[17] T. McConaghy, G. G. E. Gielen, “Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1627-1640, 2009.
[18] M. S. Bazarar, H. D. Sherali, and C. M. Shetty, “Nonlinear Programming,” Wiley, 2nd ed, 1993.
[19] S.-E. Liu, C.-P. Kung, J. Hou, “Estimate Threshold Voltage Shift in a-Si:H TFTs Under Increasing Bias Stress,” Transactions on Electron Devices, vol. 56, no. 1, pp. 56-59, 2009.
[20] F. Silveira, D. Flandre, P.G.A. Jespers, “A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” Journal of Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319, 1996.
[21] Y.-C. Tarn, P.-C. Ku, H.-H. Hsieh, L.-H. Lu, “An amorphous silicon operational amplifier and its application to 4 bit digital to analog converter,” Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1028-1035, 2010.
[22] S. Deyati, P. Mandal, “An Automated Design Methodology for Yield Aware Analog Circuit Synthesis in Submicron Technology,” IEEE International Symposium on Quality Electronic Design, pp. 1-7, Mar. 2011.
[23] F. Liu, S. Ozev, “Hierarchical analysis of process variation for mixed-signal systems,” Asia and South Pacific Design Automation Conference, vol.1, pp. 465-470, 2005.
[24] R. Jiang, W. Fu, J. M. Wang, V. Lin, C.C.-P. Chen, “Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis,” International Conference on Computer-Aided Design, pp 683-690, 2005.
[25] M. Pronath, “Circuit Design for Yield with MunEDA WiCkeD,” MunEDA Technical Forum Taiwan, 2008.
[26] J. F. Swidzinski, D. Alexander, M. Qu, M. A. Styblinski, “A Systematic Approach to Statistical Simulation of Complex Analog Integrated Circuits,” International Workshop on Statistical Metrology, pp. 86-89, 1997.
[27] J. F. Swidzinski, M. A. Styblinski, G. Xu, “Statistical Behavioral Modeling of Integrated Circuits,” International Symposium on Circuits and Systems, pp. 98-101, 1998.
[28] T. Fujita, K. Okada, H. Fujita, H. Onodera, K. Tamaru, “A Method For Linking Process-level Variability to System Performances,” Asia and South Pacific Design Automation Conference, pp. 547-551, 2000.