第三元素對於鎳矽化物形成於矽及矽碳基板之影響

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研究生：	黃仕賢 Shih-Hsien Huang
論文名稱：	第三元素對於鎳矽化物形成於矽及矽碳基板之影響 Effects of Third Element on Nickel Silicidation with Si/Si1-yCy Substrates
指導教授：	李勝偉 Sheng-Wei Lee
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 材料科學與工程研究所 Graduate Institute of Materials Science & Engineering
畢業學年度：	98
語文別：	英文
論文頁數：	104
中文關鍵詞：	熱穩定性、矽碳磊晶層、鎳、矽化物、鋁
外文關鍵詞：	Aluminium, Silicide, Nickel, Epi-SiC, Thermal stability
相關次數：	點閱：15 下載：0
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此論文的研究主題之ㄧ，為針對含鉑之鎳矽化物(Ni silicides)形成在矽碳磊晶層(epi-SiC)上之生成反應進行研究，我們發現，碳原子的存在將使得矽化鎳(NiSi)的成長動力學受到延遲，且將有效的改善矽化鎳薄膜之熱穩定性。此外，值得注意的是，在鎳矽化物形成的過程當中，我們還觀察到了不尋常的碳分布形況，實驗結果顯示，在金屬矽化(silicidation)過程，碳原子將聚集並累積在試片的中心位置，並使得矽化鎳被分成上下兩層。我們提出一個機制以解釋上述現象，並說明碳原子在鎳矽化物相變化過程中所扮演的角色，在金屬矽化過程，碳原子將會填充並占據在矽化鎳與矽化二鎳(Ni2Si)介面間，及矽化鎳晶粒邊界，並扮演一個擴散障礙(diffusion barrier)的角色，進而限制矽化鎳的晶粒成長與結塊(agglomeration)現象，並使得低電阻矽化鎳相的製程溫度範圍變得更加寬廣。
除了上述實驗，我們也針對不含鉑之鎳矽化物形成在矽碳磊晶層上之過程進行研究。此系統與含鉑系統最主要的差別在於，我們發現矽化鎳剛形成時，會在矽化二鎳層與矽基板介面處產生如金字塔狀的區域，這將使得矽化鎳完全生成時，碳原子的分布較不集中，而在含鉑的系統，矽化鎳的生成經由單一個非常平整的介面，這將使得碳原子被從矽化鎳排出時，集中的在一個平整的介面區域。另外，此實驗亦證實矽碳磊晶層在金屬矽化的過程，不但不會使應變(strain)被釋放，還會使應變進一步被增加，此結果證實，為了元件上的應用，將鎳矽化物形成於矽碳磊晶層之上是非常可行的。
最後一項實驗，我們有系統的研究鋁對於鎳矽化物形成於矽基板之影響。我們發現，鋁原子的加入將使得矽化二鎳轉換成矽化鎳的退火溫度變高，而使矽化鎳轉換成二矽化鎳(NiSi2)的退火溫度變低，並且將有效的改善矽化鎳之高溫結塊現象。我們利用了擴散障礙與晶格匹配度的角度，來解釋鋁如何使得矽化二鎳轉換成矽化鎳的退火溫度變高，而使矽化鎳轉換成二矽化鎳的退火溫度變低。此外，我們也提出一些說法以解釋鋁原子如何改善矽化鎳之高溫結塊現象。

One of this study investigates the formation of Ni(Pt) silicides on Si1-yCy (0.008≦ y≦ 0.02) epilayers grown on Si(001). The presence of C atoms retards the growth kinetics of NiSi and significantly enhances the thermal stability of NiSi thin films. In particular, an abnormal redistribution of C atoms in the NiSi thin films was observed during Ni silicidation. The NiSi layer was split into two sublayers by an obvious pile-up of C atoms. This study proposes a mechanism to elucidate this phenomenon in terms of the C solubility. C atoms accumulated at the NiSi/Si1-yCy interfaces and NiSi grain boundaries may act as diffusion barriers, effectively hindering the grain growth and agglomeration of NiSi and extending the process window of low-resistivity NiSi silicides.
In addition, the formation of Ni silicides on Si1-yCy epilayers grown on Si(001) was also investigated. It should be noted that, in our previous study, the Ni(Pt)Si layer was split into two sublayers by an obvious and narrow piles-up of C atoms. It is because the initial Ni(Pt)Si phase started with a planar structure (NiSi pyramids in this work), which effectively expelled C atoms to the planar Ni2Si/NiSi interface. In addition, HRXRD analysis shows an additional strain introduced into the Si1-yCy layers during Ni silicidation. This work demonstrates the potential of Ni silicidation on Si1-yCy epilayers for device applications.
On the other hand, the formation of Ni-Al alloy silicides on (001)Si has been systematically investigated in this study. The presence of Al atoms was found to significantly slow down the Ni2Si-NiSi phase transformation and speed up the NiSi-NiSi2 phase transformation during annealing. The addition of Al atoms also suppresses the suddenly increase in sheet resistance. We propose some explanations to depict this phenomenon and elucidate the role of Al atoms in the phase transformations.

CHAPTER 1 Introduction	1
1 An Overview	1
2 Salicide Process for CMOS Devices	3
3 Introduction to Silicides	5
4 Advantages of Nickel Silicides	12
5 High Temperature Limitations of Nickel Silicides	15
6 Channel Strain Engineering for CMOS Technology	17
7 Effects of Third Element on Ni Silicide Formation	23
References	25
CHAPTER 2 Experimental	33
1 Sheet Resistance Measurement	33
2 High Resolution X-ray Diffraction Analysis	34
3 Transmission Electron Microscope Observation	36
4 Scanning Electron Microscope Observation	37
CHAPTER 3 C Redistribution during Ni(Pt) Silicide Formation on Si1−yCy Epitaxial Layers	38
1 Motivation	38
2 Experimental Details	39
3 Results and Discussion	40
4 Conclusions	50
References	51
CHAPTER 4 The Effects of C on the Solid-Phase Reaction of NiSi1-yCy Systems	55
1 Motivation	55
2 Experimental Details	56
3 Results and Discussion	57
4 Conclusions	67
References	68
CHAPTER 5 Study of Ni/Si(001) solid-state reaction with Al addition	71
1 Motivation	71
2 Experimental Details	72
3 Results and Discussion	73
4 Conclusions	84
References	85
CHAPTER 6 Conclusions	89
1 C Redistribution during Ni(Pt) Silicide Formation on Si1−yCy Epitaxial Layers	89
2 The Effects of C on the Solid-Phase Reaction of NiSi1-yCy Systems	89
3 Study of Ni/Si(001) solid-state reaction with Al addition	90

                                

[1] J. A. Kittl, Q. Z. Hong, “Self-aligned Ti and Co silicides for high performance sub-0.18 μm CMOS technologies”, Thin Solid Films, 320, 110 (1998).
[2] F. Deng, R. A. Johnson, P. M. Asbeck, S. S. Lau, W. B. Dubbelday, T. Hsiao, “Salicidation process using NiSi and its device application”, J. Woo, J. Appl. Phys., 81, 8047 (1997).
[3] J. P. Gambino, E. G. Colgan, “Silicides and ohmic contacts”, Mater. Chem. Phys., 52, 99 (1998).
[4] C.-P. Chao, K. E. Violette, S. Unnikrishnan, M. Nandakumar, R. L. Wise, J. A. Kittl, Q.-Z. Hong, I.-C. Chen, “Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 μm CMOS technologies”, IEDM Tech. Dig., 103 (1997).
[5] J. A. Kittl, Q. Z. Hong, H. Yang, N. Yu, S. B. Samavedam, M. A. Gribelyuk, “Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2”, Thin Solid Films, 332, 404 (1998).
[6] J. A. Kittl, K. Opsomer, C. Torregiani, C. Demeurisse, S. Mertens, D. P. Brunco, M. J. H. Van Dal, A. Lauwers, “Silicides and germanides for nano-CMOS applications”, Mater. Sci. Eng. B, 154, 144 (2008).
[7] S. P. Murarka, “Silicide thin films and their applications in microelectronics”, Intermetallics, 3, 173 (1995).
[8] E. G. Colgan, J. P. Gambino, Q. Z. Hong, “Formation and stability of silicides on polycrystalline silicon”, Mater. Sci. Eng., R16, 43 (1996).
[9] M. Diale, C. Challens, E. C. Zingu, “Cobalt self-diffusion during cobalt silicide growth”, Appl. Phys. Lett., 62, 943 (1993).
[10] P. Liu, T. C. Hsiao, J. C. S. Woo, “A low thermal budget self-aligned Ti silicide technology using germanium implantation for thin-film SOI MOSFET’s”, IEEE Trans. Electron Devices, 45, 1280 (1998).
[11] E. Gerritsen, “Spike anneal: RTP processing at reduced thermal budget with applications to TiSi formation towards 0.1-μm linewidths”, Microelectron. Eng., 50, 147 (2000).
[12] R. W. Mann, L. A. Clevenger, “The C49 to C54 phase transformation in TiSi2 Thin Films”, J. Electrochem. Soc., 141, 1347 (1994).
[13] G. L. Miles, R. W. Mann, J. E. Bertseh, “TiSi2 phase transformation characteristics on narrow devices”, Thin Solid Films, 290, 469 (1996).
[14] A. Lauwers, Q. F. Wang, B. Deweerdt, K. Maex, “Ti/Co bilayers in salicide technology electrical evaluation”, Appl. Surf. Sci., 91, 12 (1995).
[15] J. A. Kittl, W. T. Shiau, Q. Z. Hong, D. Miles, “Salicides: materials, scaling and manufacturability issues for future integrated circuits”, Microelectron. Eng., 50, 87 (2000).
[16] T. Morimoto, T. Ohguro, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, I. Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, H. Iwai, “Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI”, IEEE Trans. Electron Devices, 42, 915 (1995).
[17] A. Lauwers, J. A. Kittl, M. J. H. Van Dal, O. Chamirian, M. A. Pawlak, M. de Potter, R. Lindsay, T. Raymakers, X. Pages, B. Mebarki, T. Mandrekar, K. Maex, “Ni based silicides for 45 nm CMOS and beyond”, Mater. Sci. Eng. B, 114. 29 (2004).
[18] B. Imbert, R. Pantel, S. Zoll, M. Gregoire, R. Beneyton, S. del Medico, O. Thomas, “Nickel silicide encroachment formation and characterization”, Microelectron. Eng., 87, 245 (2010).
[19] M. Sinha, E. F. Chor, Y. C. Yeo, “Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation”, Appl. Phys. Lett., 92, 222114 (2008).
[20] T. Ohguro, S.-i. Nakamura, M. Koike, T. Morimoto, A. Nishiyama, Y. Ushiku, T. Yoshitomi, M. Ono, M. Saito, H. Iwai, “Analysis of resistance behavior in Ti and Ni-salicided polysilicon films”, IEEE Trans. Electron Devices, 41, 2305 (1994).
[21] H. Iwaia, T. Ohguro, S.-i. Ohmia, “NiSi salicide technology for scaled CMOS”, Microelectron. Eng., 60, 157 (2002).
[22] X.-P. Qu, Y.-L. Jiang, G.-P. Ru, F. Lu, B.-Z. Li, C. Detavernier, R .L. Van Meirhaeghe, “Thermal stability, phase and interface uniformity of Ni-silicide formed by Ni–Si solid-state reaction”, Thin Solid Films, 462, 146 (2004).
[23] D. Deduytsche, C. Detavernier, R. L. Van Meirhaeghe, C. Lavoie, “High-temperature degradation of NiSi films: Agglomeration versus NiSi2 nucleation”, J. Appl. Phys., 98, 033526 (2005).
[24] D. Ma, D. Z. Chi, M. E. Loomans, W. D. Wang, A. S. W. Wong, S. J. Chua, “Kinetics of NiSi-to-NiSi2 transformation and morphological evolution in nickel silicide thin films on Si(001)”, Acta Mater., 54, 4905 (2006).
[25] P. Revesz, L. R. Zheng, L. S. Hung, J. W. Mayer, “Morphological degradation of TiSi2 on (100) silicon”, Appl. Phys. Lett., 48, 1591 (1986).
[26] F. F. Zhao, J. Z. Zheng, Z. X. Shen, T. Osipowicz, W. Z. Ga, L. H. Chan, “Thermal stability study of NiSi and NiSi2 thin films”, Microelectron. Eng., 71, 104 (2004).
[27] R. Tanabe, T. Yamasaki, Y. Ashizawa, H. Oka, “Analysis of nano-scale MOSFET including uniaxial and biaxial strain”, J. Comp. Electron, 6, 49 (2007).
[28] K. Rim, R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen, S. Christansen, J. Chu, K. Jenkins, T. Kanarsky, S. Koester, B. H. Lee, K. Lee, V. Mazzeo, A. Mocuta, D. Mocuta, P. M. Mooney, P. Oldiges, J. Ott, P. Ronsheim, R. Roy, A. Steegen, M. Yang, H. Zhu, M. Ieong, H.-S. P. Wong, “Strained Si CMOS (SS CMOS) technology: opportunities and challenges”, Solid-State Electron., 47, 1133 (2003).
[29] K. Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFET’s”, IEEE Trans. Electron Devices, 47, 1406 (2000).
[30] K. W. Ang, K. J. Chui, V. Blimetsov, A. Du, N. Balasubramanian, M. F. Li, G. Samudra, Y.-C. Yeo, “Enhanced performance in 50 nm n-MOSFETs with silicon-carbon source/drain regions”, Tech. Dig.-Int. Electron Devices Meet., 1069 (2004).
[31] H. Yin, Z. Ren, H. Chen, J. Holt, X. Liu, J. W. Sleight, K. Rim, V. Chan, D. M. Fried, Y. H. Kim, J. O. Chu, B. J. Greene, S.W. Bedell, G. Pfeiffer, R. Bendernagel, D. K. Sadana, T. Kanarsky, C. Y. Sung, M. Ieong, G. Shahidi, “Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates”, Tech. Dig.-VLSI, 76 (2006).
[32] K.-W. Ang, K.-J. Chui, H.-C. Chin, Y.-L. Foo, A. Du, W. Deng, M.-F. Li, G. Samudra, N. Balasubramanian, Y.-C. Yeo, “50 nm silicon-on-insulator n-MOSFET featuring multiple stressors: silicon-carbon source/drain regions and tensile stress silicon nitride liner”, Tech. Dig.-VLSI, 90 (2006).
[33] Y.-C. Yeo, Semicond. Sci. Technol., “Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions”, 22, S177 (2007).
[34] C.-H. Ge, C.-C. Lin, C.-H. KO, C.-C. Huang, Y.-C. Huang, B.-W. Chan, B.-C. Pemg, C.-C. Sheu, P.-Y. Tsai, L.-G. Yao, C.-L. Wu, T.-L. Lee, C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering”, Tech. Dig.-Int. Electron Devices Meet., 73 (2003).
[35] K. Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFET’s”, IEEE Trans. Electron Devices, 47, 1406 (2000).
[36] T. Tezuka, N. Sugiyama, T. Mizuno, S. Takagi, “Novel fully-depleted SiGe-on-insulator p-MOSFETs with high-mobility SiGe surface channels”, Tech. Dig.-Int. Electron Devices Meet., 946 (2001).
[37] T. Komoda, A. Oishi, T. Sanuki, K. Kasai, H. Yoshimura, K. Ohno, M. Iwai, M. Saito, F. Matsuoka, N. Nagashima, T. Noguchi, “Mobility improvement for 45 nm node by combination of optimized stress control and channel orientation design”, Tech. Dig.-Int. Electron Devices Meet., 217 (2004).
[38] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, “A 90-nm logic technology featuring strained-silicon”, IEEE Trans. Electron Devices, 51, 1790 (2004).
[39] J. Demeulemeester, D. Smeets, C. Van Bockstael, C. Detavernier, C. M. Comrie, N. P. Barradas, A. Vieira, A. Vantomme1, “Pt redistribution during Ni(Pt) silicide formation”, Appl. Phys. Lett., 93, 261912 (2008).
[40] D. Lee, K. Do, D.-H. Ko, S. Choi, J.-H. Ku, C.-W. Yang, “The effects of Ta on the formation of Ni-silicide in Ni0.95xTax0.05/Si systems”, Mater. Sci. Eng. B, B114, 241 (2004).
[41] Y. Setiawan, P. S. Lee, C. W. Tan, K. L. Pey, “Effect of Ti alloying in nickel silicide formation”, Thin Solid Films, 504, 153 (2006).
[42] W. Huang, L.-C. Zhang, Y.-Z. Gao, H.-Y. Jin, “The improvement of thermal stability of nickel silicide by adding a thin Zr interlayer”, Microelectron. Eng., 83, 345 (2006).
[43] W. Huang, L. Zhang, Y. Gao, H. Jin, “Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi”, Microelectron. Eng., 84, 678 (2007).
[44] W. Huang, Y. L. Min, G. P. Ru, Y. L. Jiang, X. P. Qu, B. Z. Li, “Effect of erbium interlayer on nickel silicide formation on Si(100)”, Appl. Surf. Sci., 254, 2120 (2008).
[45] D. Mangelinck, J. Y. Dai, J. S. Pan, S. K. Lahiri, “Enhancement of thermal stability of NiSi films on (100)Si and (111)Si by Pt addition”, Appl. Phys. Lett., 75, 1736 (1999).
[46] C. Detaverniera, C. Lavoie, “Influence of Pt addition on the texture of NiSi on Si(001)”, Appl. Phys. Lett., 84, 3549 (2004).
[47] M. Sinha, E. F. Chor, Y.-C. Yeoa, “Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation”, Appl. Phys. Lett., 92, 222114 (2008).
[48] A. T.-Y. Koh, R. T.-P. Lee, A. E.-J. Lim, D. M.-Y. Lai, D.-Z. Chi, K.-M. Hoe, N. Balasubramanian, G. S. Samudra, Y.-C. Yeo, “Nickel-aluminum alloy silicides with high aluminum content for contact resistance reduction and integration in n-channel field-effect transistors”, J. Electrochem. Soc., 155, H151 (2008).
[49] O. Nakatsuka, K. Okubo, A. Sakai, M.Ogawa,Y. Yasuda, S. Zaima, “Improvement in NiSi/Si contact properties with C-implantation”, Microelectron. Eng., 82, 479 (2005).
[50] V. Machkaoutsan, S. Mertens, M. Bauer, A. Lauwers, K. Verheyden, K. Vanormelingen, P. Verheyen, R. Loo, M. Caymax, S. Jakschik, D. Theodore, P. Absil, S. G. Thomas, E. H. A. Granneman., “Improved thermal stability of Ni-silicides on Si:C epitaxial layers”, Microelectron. Eng., 84, 2542 (2007).

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