正交分頻多工器主要是利用所有的子載波正交特性進行調變，並利用循環字首(cyclic prefix)來消除符元間干擾及載波間干擾，而濾波器組多載波(Filter Bank Multicarrier, FBMC)傳輸技術只需要維持和相鄰子載波之間的正交特性即可。因此，為了保持濾波器組多載波系統正交特性和提高頻寬使用率，將會使用偏移正交振幅調變(Offset Quadrature Amplitude Modulation, OQAM)。有鑒於採樣濾波器的良好振幅響應和微小的旁瓣干擾。使用頻率採樣濾波器，將偏移正交振幅調變和頻率採樣濾波器组結合，我們將不再需要使用循環字首進而得到更好的頻寬使用率。
在濾波器組的部分，傳送端為合成濾波器组(Synthesis filter bank)，可以得到一個很直觀的演算法，然後可用反離散傅立葉轉換實現。接收端為分析濾波器組(Analysis filter bank)，則用離散傅立葉轉換實現。濾波器组可拆解成多相位網路濾波器與快速傅立葉轉換處理器，在系統所需速度不快的情況下，採用了記憶體式快速傅立葉轉換處理器，將傳送端與接收端的多相位網路濾波器與快速傅立葉轉換處理器整合。
本論文使用同質性可組態記憶體式快速傅立葉轉換處理器，重新檢視基數2快速傅立葉轉換演算法，並重新探討傳統的信號流程圖，進而發展出另一種信號流程圖的表示法，其中我們證明了輸入資料的改變，並不會喪失原有的快速傅立葉轉換數學運算性。因此，這樣的信號流程圖表示法，可以容易地得到一同質性之運算並行式結構的可組態式快速傅立葉轉換處理器之架構，藉此提高吞吐量。同時仍保有記憶體式架構優於管線式架構面積小的優勢，提升原有記憶體式架構之速度，且易於控制。

In OFDM, IFFT and cyclic prefix to avoid the circular convolution aliasing are usually used to ensure the orthogonality for all subchannels, while FBMC only requires orthogonality with adjacent subchannels. In order to fully exploit channel bandwidth, modulations in the subchannels must adapt to the neighbor orthogonality constraint, so Offset Quadrature Amplitude Modulation (OQAM) is used for this purpose. Frequency selective filter is accomplished by using longer and spectrally well-shaped prototype filters, and because of frequency selective filter, the sidelobe levels are lower comparing to OFDM. Combination of filter banks and OQAM modulation result in no need for guard time or cyclic prefix like OFDM, leading to higher bandwidth efficiency. In general, this technique is called Filter Bank Multicarrier (FBMC) technique.
In FBMC system, the transmitter is called synthesis filter bank. We can get an intuitive algorithm, implemented by Inverse Discrete Fourier Transform. Then, the receiver is called analysis filter bank, implemented by using Discrete Fouier Transform. Filter banks consists of Polyphase Network (PPN) filter and FFT processor, we. Because the condition of the system speed demand is not fast, we choose the memory-based IFFT/FFT processor. Finally, PPN filter and IFFT/FFT processor are combined in transmitter and receiver.
This dissertation presents a reconfigurable homogeneous memory-based FFT processor architecture. Specifically, this thesis reinvestigates a radix-2 FFT algorithm and rearranges an alternative signal flow graph (SFG) from conventional SFGs. By developing the alternative SFG, this thesis proves that the altered permutation of input data can maintain the original functionality of FFT computation. Consequently, the alternative SFG is readily realized as the architecture of homogeneous parallel structure with multiple processing elements to increase throughput. However, the proposed design retains the advantage of a small area for the memory-based architecture, and achieves the goals of fast operation and ease of control.

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