自對準矽奈米線金氧半場效電晶體之研製｜國立中央大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	顏瑋廷 Wei-Ting Yen
論文名稱：	自對準矽奈米線金氧半場效電晶體之研製 A Self-Aligned Nanowire MOSFET
指導教授：	李佩雯 Pei-Wen Li
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	94
語文別：	英文
論文頁數：	43
中文關鍵詞：	自對準、矽奈米線
外文關鍵詞：	Silicon nanowires, Self-aligned
相關次數：	點閱：8 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在此篇論文裡，使用快速熱退火去形成鎳化矽的製程被研究。然後鎳化矽被應用於新穎的元件結構裡--自對準奈米線金氧半場效電晶體。自對準奈米線電晶體被製作在70奈米厚的絕緣層上矽的基版上，具有先進製程模組，包含凹陷式氮化矽間隙壁、完全鎳化矽源極與汲極、自對準多晶矽閘。為了讓元件在薄的絕緣層上矽的基版上，獲得低串聯電阻，利用完全鎳化矽源/汲極與最佳化間隙壁寬度製程可獲取效益。因為區域矽氧化法被整合在奈米線電晶體製程裡，我們不需用電子束微影去做精確的對準，即可獲得超窄的閘堆疊結構，使得自對準多晶矽閘技術有效的改善製程量率。由於熱磷酸濕蝕刻在氮化矽與矽之間有很高的選擇比，因此熱磷酸濕蝕刻被使用來實現凹陷式間隙壁。藉由凹陷式間隙壁，多晶矽化金屬的邊際效應被增強，導致於片電阻值被進一步的減少。最後，元件的效能被量測與分析。

In this thesis, the formation of NiSi silicide using rapid thermal annealing is investigated. The NiSi salicidation process is, then, incorporated into the fabrication of novel self-aligned nanowire MOSFET devices structure. A self-aligned nanowire MOSFET fabricated on a 70-nm-thick SOI wafer, features advanced process modules including recessed nitride spacer, fully silicided (NiSi) source/drain, and self-aligned poly silicon gate. In the pursuit of low series resistance in a thin SOI, it is critical to optimize spacer width and utilize fully-silicide S/D. Since LOCOS process is integrated in a nanowire MOSFET process flow, one doesn’t require e-beam lithography to do precise alignment for ultra narrow gate stacked structure. A self-aligned poly gate technology is utilized to improve manufacturing yield efficiently. A recessed spacer structure is carried out using hot phosphoric acid etching, which is highly selective between Si3N4 and Si. Edge effects of Ni polycide formation are enhanced by such recessed spacer and result in Rs reduction further. Finally, the device performance is evaluated.

Contents
Chapter 1. Introduction....................................................................................................... 1
1-1. History.............................................................................................................. 1
1-2. SOI-MOSFET.................................................................................................. 2
1-3. Experimental motivation and objective........................................................... 5
Chapter 2. Silicidation......................................................................................................... 7
2-1. History.............................................................................................................. 7
2-2. Salicidation development................................................................................. 7
2-3. NiSi film properties......................................................................................... 9
2-4. NiSi process....................................................................................................10
2-5. NiSi sheet resistance...................................................................................... 12
2-6. Back-end process............................................................................................14
2-7. Application.....................................................................................................15
Chapter 3. Nanowire MOSFET Fabrication Process........................................................ 18
3-1. Device structure........................................................................................... 18
3-2. Main process flow........................................................................................ 19
3-3. Devices fabrication process......................................................................... 20
Chapter 4. Experimental results and discussion................................................................ 28
4-1. Short channel effects.................................................................................... 28
4-2. Device operation mode................................................................................ 30
4-3. Reduced driving current.............................................................................. 32
4-4. Temperature dependence..............................................................................36
Chapter 5. Conclusion....................................................................................................... 40
References......................................................................................................................... 41

                                

[1] S. E. Thompson et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, p. 1790. 2004.
[2] C. Y. Chang et. al., ULSI Devices, Wiley, New York, 2000.
[3] M. Heuser et. al., “Fabrication of wire-MOSFETs on silicon-on-insulator substrate,” Microelectronic Engineering, vol. 61, p. 613. 2002.
[4] D. Connelly et al., “Ultra-Thin-Body Fully Depleted SOI Metal Source/Drain n-MOSFETs and ITRS Low-Standby-Power Targets through 2018,” IEDM Technical Digest, 2005.
[5] H. Park et al., “High performance CMOS devices on SO1 for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering,” IEDM Technical Digest, p. 635. 2003.
[6] M. Schmidt et al., “Nickel-silicide process for ultra-thin-body SOI-MOSFETs,” Microelectronic Engineering, vol. 82, p. 497. 2005.
[7] H. Iwai et. al., “NiSi salicide technology for scaled CMOS,” Microelectronic Engineering, vol. 60, p. 157. 2002.
[8] T. Morimoto et. al., “A NiSi salicide technology for advanced logic devices,” IEDM Technical Digest, p. 653. 1991.
[9] T. Ohguro et. al., “Analysis of Resistance Behavior in Ti- and Ni-Salicided Polysilicon Films,” IEEE Trans. Electron Devices, vol. 41, p. 2305. 1994.
[10] F. Deng et al., “Salicidation process using NiSi and its device application,” J. Appl. Phys. vol. 81, p. 8047. 1997.
[11] T. Morimoto et. al., “ Self-aligned nickelmono silicide technology for high speed deep submicrometer logic CMOS ULSI ,” IEEE Trans. Electron Devices, vol. 42, p. 915. 1995.
[12] F. Deng et al., “Salicidation process for 400 Å fully-depleted SOI-MOSFET using nickel,” Proceedings of 1997 IEEE International SOI Conferences, p. 22. 1997.
[13] K. G. Anil et al., “CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach,” Symp. VLSI Tech. Dig. p. 198. 2005.
[14] T. Ghani et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” IEDM Technical Digest, p. 978. 2003
[15] C. Lavoiei et. al., “Towards implementation of a nickel silicide process for CMOS technologies,” Microelectronic Engineering, vol. 70, p. 144. 2003.
[16] S. Verdonckt et. al., “ SiGe-channel heterojunction p-MOSFET,” IEEE Trans. Electron Devices, vol. 41, p. 90. 1994.
[17] P. C. Yeh et. al., “Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low voltage CMOS technology,” IEEE Trans. Electron Devices, vol. 42, p.1605.1995.
[18] H. Wang et. al., “The behavior of narrow-width SOI MOSFET’s with mesa isolation ,” IEEE Trans. Electron Devices, vol. 47, p.593. 2000.
[19] D. A. Neamen, Semiconductor Physics and Devices, McGraw-Hill, 2002
[20] S. H. Zaidi et. al., “Multiple nanowire gate field effect transistors,” IEEE Nano Devices, p. 189. 2001.
[21] J. D. Plummer et al., Silicon VLSI Technology, Prentice-Hall, Inc., 2000
[22] C. Sorin et. al., “Introduction to silicon on insulator materials and devices,” Microelectronic Engineering, vol.39, p.145.1997.
[23] H. Fritz et. al., “Very small MOSFET’s for low-temperature operation,” IEEE Trans. Electron Devices, vol. 24, p. 218. 1977.
[24] O. Leistiko et. al., “Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. 12, p. 248. 1965.
[25] N. Lindert et. al., “Sub-60-nm quasi-planar FinFETs fabricated using a simplified process,” IEEE Electron Device Lett., vol. 22, p. 487. 2001.

簡易檢索 / 詳目顯示

相關論文