DVB-S2訊號符碼時間同步演算法之研究與硬體實現

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研究生：	徐巧庭 Chiao-Ting Hsu
論文名稱：	DVB-S2訊號符碼時間同步演算法之研究與硬體實現 Implementation of DVB-S2 Symbol Timing Synchronization Algorithm
指導教授：	陳逸民
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 通訊工程學系 Department of Communication Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	中文
論文頁數：	81
中文關鍵詞：	第二代數位衛星廣播、Gardner時間錯誤檢測器、符碼時間同步器、數位訊號處理器
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隨著數位衛星通訊技術的快速發展下，高資料率通訊技術在衛星通訊領域成為熱門的研究課題與技術發展方向。衛星通訊系統已廣泛應用於數位衛星電視和數據的傳輸標準等領域。DVB-S2標準提供高的頻譜效率和強大的錯誤修正能力，整體系統設計在低訊雜比(SNR)的環境下仍然能運作，以適應不同傳輸環境的應用。
本論文主要研究DVB-S2接收端之符碼時間同步問題，評估性能以實現硬體設計。其中，針對盲蔽式時間同步方法進行探討，此方法不需要決策數據和pilot訊號，也不需要先做載波同步，就能回復符碼訊號。優點是能夠保持頻譜利用率，缺點是收斂數度較慢。最後，為滿足高通量的需求，提出了平行化訊號處理之架構，其中包括高通量的匹配濾波器和高通量的符碼時間同步器。

With the rapid development of digital satellite communication technology, high data rate communication has become a popular topic and technological direction in the satellite communication. Satellite communication systems have been widely used in areas such as digital satellite television and data transmission standards. The DVB-S2 standard provides high spectrum efficiency and powerful error correction capabilities, allowing the overall system design to operate effectively in low signal-to-noise ratio (SNR) environments, thus adapting to various transmission environments.
This thesis primarily focuses on the study of the symbol timing synchronization problem in the DVB-S2 receiver, with the aim of evaluating its performance for hardware implementation. In particular, the thesis explores blind timing synchronization methods, which do not require decision data or pilot signals, and do not necessitate carrier synchronization prior to recovering symbol signals. The advantage of this approach is its ability to maintain spectrum efficiency, while its drawback is slower convergence. Lastly, to meet the requirements of high throughput, an architecture for parallel signal processing is proposed, incorporating high-throughput matched filters and high-throughput symbol timing synchronizers.

摘要    i
ABSTRACT    ii
誌謝    iii
目錄    iv
圖目錄    vii
表目錄    xi
第一章、    緒論    1
1    研究動機和背景    1
2    論文架構    1
第二章、    系統傳收架構介紹    2
1    DVB-S2傳送端流程    2
2    Stream Adapter    2
2.1    Base-Band Header insertion    3
2.2    Padder    3
2.3    Baseband Scrambler    4
3    Forward Error Correction (FEC) Encoder    5
3.1    BCH and LDPC Code    5
3.2    Bit-Interleaver    5
4    Bit Mapping    7
4.1    QPSK    7
4.2    8PSK    8
4.3    16APSK    8
4.4    32APSK    9
5    Physical Layer (PL) Framing    10
5.1    Physical Layer (PL) Header    11
5.2    Physical Layer (PL) Scrambling    11
6    基頻傳送端    12
7    基頻接收端    14
第三章、    符碼時間同步演算法    16
1    內部接收器    16
2    匹配濾波器(The Matched Filter)    17
3    符碼時間同步器(Symbol Timing Synchronizer)    18
3.1    符碼時間同步演算法    22
3.2    Farrow內插器(Farrow Interpolator)    23
3.3    Gardner Timing Error Detector (Gardner TED) 演算法    25
3.4    迴路濾波器(Loop filter)    26
3.5    內插控制器(Interpolation Controller)    28
4    模擬情境    29
4.1    Band-Limited Additive White Gaussian Noise (AWGN)情境    29
4.2    取樣頻率偏差(Sampling Frequency Offset)    30
第四章、    硬體架構實現    31
1    匹配濾波器架構    31
2    符碼同步架構    34
2.1    Farrow內插器    35
2.2    時間錯誤檢測器(Gardner TED)    38
2.3    迴路濾波器(Loop filter)    38
2.4    時間控制器(Timing Controller)    39
3    高通量平行匹配濾波器架構    41
4    高通量平行符碼同步器架構    43
4.1    平行化Farrow內插器    44
4.2    內插控制器(Interpolation Controller)    48
第五章、    性能評估與硬體驗證    50
1    模擬分析    50
2    性能評估    54
3    硬體驗證結果    58
3.1    硬體資源利用率    58
3.2    高通量架構硬體資源利用率    59
3.3    符碼時間同步器實現結果    60
第六章、    結論    65
1    總結論文的主要內容和貢獻    65
2    提出未來工作的建議和展望    65
參考文獻    66

                                

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