混合式加法器設計｜國立中央大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	張劭鍇 Shao-kai Chang
論文名稱：	混合式加法器設計 Hybrid Adder Designs
指導教授：	魏慶隆 Chin-Long Wey 謝韶徽 Shao-Hui Shieh
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	中文
論文頁數：	44
中文關鍵詞：	混合式加法器、前瞻進位加法器、跳躍進位加法器、平行預算加法器
外文關鍵詞：	Parallel Prefix adder, Carry Skip Adder, Carry lookahead adder, Hybrid Adder
相關次數：	點閱：6 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文提出一個快速的六十四位元加法器﹐使用動態的邏輯電路及傳輸閘的架構﹐應用於Brent-Kung Tree。此加法器為混合式的加法器架構，其採用前瞻進位單元和多工器且具有8個邏輯閘階層。由模擬結果顯示，混合加法器在最壞情況的延遲為298ps，而使用的製程技術為TSMC 0.18 um 2P6M CMOS technology，電源電壓為1.8伏特。同時我們也在其他的先進製程中模擬，模擬結果顯示，混合加法器在最壞情況的延遲為110ps，而使用的製程技術為UMC 90 nm 1P9M CMOS Low-K technology，電源電壓為1伏特。

The thesis presents a fast 64-bit adder based on domino logics and pass transmission gates in the Brent-Kung Tree. The proposed adder uses a hybrid adder of Carry Look-Ahead and MUX architecture in 8 logic levels. Simulation results show that the proposed hybrid adder achieves a delay of 298ps, where the TSMC 0.18 um 2P6M CMOS technology with the supply voltage of 1.8V. Based on UMC 90 nm 1P9M CMOS Low-K technology with the supply voltage of 1V, the proposed 64-bit hybrid adder achieves a delay of 110ps with 6mW power dissipation.

摘要                i
Abstract                ii
致謝                iii
圖目錄                vi
表目錄                viii
一、前言                1
1.1研究動機            1
1.2論文大綱            1
二、預備知識            2
2.1 Carry Look-Ahead Addition    2
2.2 Ling’s Adder            4
2.3 Parallel-Prefix (P-P) Addition    5
2.3.1 Kogge-Stone Tree        5
2.3.2 Brent-Kung Tree        6
2.3.3 Han-Carson            6
2.3.4 Sklansky            7
2.3.5 總結            7
2.4 Fan-out of 4            8
三、我們提出的加法器架構        10
3.1 回顧以前的加法器        10
3.2 新加法器的架構            10
3.2.1 Hybrid Adder Unit        12
3.2.2應用於六十四位元加法器        14
3.2.3進位的方式            16
3.2.4 新架構和可組態加法器        17
3.3 總結新架構的優點        21
四、電路設計            23
4.1 Domino Logics            23
4.2 Transmission Gates (MUX)    24
4.3 Critical Path and Driving Power    27
4.4 Floorplaning            30
五、模擬分析以比較            33
5.1模擬分析            33
5.2 Layout            33
5.3 比較                39
六、結論與未來工作            42
6.1結論                42
6.2未來工作            42
參考文獻                43

                                

[1] I. Koren, Computer Arithmetic Algorithms, Prentice-Hall, Inc., New Jersey, 1993.
[2] K. Huang, Computer Arithmetic: Principles, Architecture, and Design, Wiley & Sons, Inc., 1979.
[3] J.C. Lo, "A Fast Binary Adder with Conditional Carry Generation," IEEE Trans. on Computers, pp. 248-253, Feb. 1997.
[4] S. Naffziger, " A Sub-Nanosecond 0.5 μm 64 b Adder Design, " IEEE Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 210–211, February 1996.
[5] S. Kao, R. Zlatanovici, B. Nikolic, "A 240ps 64b Carry-Lookahead Adder in 90nm CMOS, " IEEE Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 1735-1744, Feb. 2006.
[6] S. Kao, R. Zlatanovici, B. Nikolic, "Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example," IEEE Journal of Solid-State Circuits(JSSC), vol. 44, no. 2, pp. 569-583 , February 2009
[7] J. Park, H. C. Ngo, J. A. Silberman, and S. H. Dong, "470 ps 64 bit Parallel Binary Adder, " Symposium on VLSI Circuits Digest of Technical Papers, pp. 192-193, June 2000.
[8] H. Ling, "High Speed Binary Adder, " IBM J. Res. Develop., vol. 25, no. 3, pp. 156-166, May 1981.
[9] R. W. Doran, "Ariants of an Improved Carry-Lookahead Adder," IEEE Trans. on Computers, vol. 37, pp. 1110-1113, September 1988.
[10] S. Vassiliadis, "Recursive Equations for Hardwired Binary Adders," International Journal of Electronics, vol. 67, no. 2, pp. 201-13, August 1989.
[11] S. Mathew, R. Krishnamurthy, M. Anders, R. Rios, K. Mistry,K. Soumyanath, "Sub-500-ps 64-b ALUs in 0.18μm SOI/Bulk CMOS: Design and Scaling Trend," IEEE Journal of Solid-State Circuits(JSSC), pp. 1636-1646, November 2001.
[12] J. Kim, K. Lee and H. J. Yoo, "A 372ps 64-bit Adder using Fast Pull-up Logic in 0.18μm CMOS," International Symposium on Circuits and Systems(ISCAS), pp. 4-16, September 2006.
[13] S. Sun, Y. Han, X. Guo, K. H. Chong, L. M. Murchie, and C. Sechen, "409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18μm CMOS," IEEE Computer Society Annual Symposium, pp. 52-58, May 2005.
[14] D. Stasiak, F. Mounes-Toussi, S.N. Storino, "A 440-ps 64-bit Adder in 1.5-V 0.18 μm Partially Depleted SOI Technology," IEEE Journal of Solid-State Circuits(JSSC), vol. 33, no. 10, pp. 1546-1552, October 2001.
[15] J. Park, H. Ngo, J. Silberman, S. Dhong, "470-ps 64-bit Parallel Binary Adder," Symposium on VLSI Circuits Digest of Technical Papers, pp. 192-193, June 2000.
[16] S. Lee, R. Woo, H. Yoo, "480 ps 64-bit Race Logic Adder," Symposium on VLSI Circuits Digest of Technical Papers, pp. 27-28, June 2001.
[17] A. Neve, H. Schettler, T. Ludwig, D. Flandre, "Power Delay Product Minimization in High-Performance 64-bit Carry-Select Adders," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, on. 3, pp. 235-244, March 2004.
[18] J. Kim, R. Joshi, C. Chuang, K. Roy, "SOI-Optimized 64-bit High-Speed CMOS Adder Design," Symposium on VLSI Circuits Digest of Technical Papers, pp. 122-125, June 2002.

簡易檢索 / 詳目顯示

相關論文