本論文係以TSMC 0.18 μm CMOS製程，研製應用於超寬頻(UWB)系統之寬頻低雜訊放大器，以及應用於微波存取全球互通系統(WiMax)利用三角積分調變器(Delta-Sigma Modulator)之分數型頻率合成器。
第一部分為寬頻低雜訊放大器之研製，此電路使用兩級串接式架構設計，在頻寬設計上利用橋接式並串峰化(Bridged-shunt-series peaking)架構，實現上的確造成不錯的頻寬延展效果並且兼顧增益平坦特性；在寬頻輸入匹配上使用電阻性回授的方式結合高通網路不僅可達成良好的匹配效果，且可同時具有不錯的雜訊指數特性。量測之最大功率增益發生於3 ~ 4 GHz，其值為14.2 dB，增益平坦度小於1 dB之頻寬為2.5 ~ 9.3 GHz，而3 dB頻寬為2.2 ~ 11 GHz；輸入及輸出反射損耗在整個寬頻範圍內分別大於9 dB及10 dB；隔離度大於32 dB；量測之雜訊指數其值為3.4 ~ 4.5 dB，而平均雜訊指數小於4 dB；輸入1 dB壓縮點及三階截斷點分別大於–8.5 dBm及–0.5 dBm，總功率消耗為30 mW。
第二部分為三角積分調變分數型頻率合成器之研製，此電路中包含了互補式LC交錯耦合壓控振盪器(VCO)、三角積分調變器(DSM)、多模數除頻器(MMD)、真實單一相位時脈(TSPC)除頻器、相位頻率檢測器(PFD)、充電泵(CP)以及迴路濾波器(LF)。在VCO的部份，為了防止製程變異所導致振盪頻率偏移，加入了二進位加權開關；在DSM的方面，為了避免電路的不穩定發生，使用多級雜訊整型(MASH)架構。量測之VCO調諧範圍從2.42 ~ 2.69 GHz，輸出功率為–1.5 ~ 0.1 dBm，相位雜訊在偏移主頻100 KHz和1 MHz分別為–88.7 ~ –95.3 dBc/Hz以及–117.1 ~ –122.9 dBc/Hz，直流功率消耗為4.14 mW。此壓控振盪器之FOM最佳值為184.9 dBc/Hz。

The thesis presents an Ultra Wideband low noise amplifier and a Fractional-N frequency synthesizer with delta-sigma modulator for WiMax applications, which are implemented in TSMC 0.18-μm CMOS technology.
The first section is the design of a broadband low noise amplifier, and the circuit adopts two-stage cascaded scheme. By adopting the bridged-shunt-series peaking technique, both the maximum bandwidth and the maximally flat response can be achieved in a way. The LC high-pass filter and the typical narrow band designs with a feedback resistor construct input matching network, which provides good input match while contributing a small amount in NF degradation. The measured power gain reaches its maximum value of 14.2 dB at around 3 to 4 GHz, and remains 1 dB flatness from 2.5 to 9.3 GHz. The 3-dB bandwidth is occurred from 2.2 to 11 GHz. The measured input and output return loss are larger than 9 dB and 10 dB over the entire UWB band. The measured isolation is greater than 32 dB. The measured noise figure is from 3.4 to 4.5 dB, and its average value is lower than 4 dB across the band of interested. Finally, the measured P1dB and IIP3 are better than -8.5 dBm and -0.5 dBm, respectively. The total power consumption is 30 mW.
The second section is the design of a Fractional-N frequency synthesizer with delta-sigma modulator, which includes a complementary LC cross-coupled voltage controlled oscillator (VCO), a delta-sigma modulator (DSM), a multi-modulus divider (MMD), a true single phase clock (TSPC) divider, a phase frequency detector (PFD), a charge pump (CP) and a loop filter (LF). In the VCO design, the binary weighted band switching capacitors are used to calibrate the frequency drifting under process variations. Besides, by adopting the multi-stage noise shaping (MASH) architecture of DSM avoids unstable condition. The measured VCO tuning range is from 2.42 to 2.69 GHz, and yields an output power from -1.5 to 0.1 dBm. The measured close loop phase noise under band switching are from -88.7 to -95.3 dBc/Hz and -117.1 to -122.9 dBc/Hz at 100 kHz offset and 1 MHz offset, respectively. The dc power consumption of VCO is 4.14 mW, and its associated FOM reaches the best value of 184.9 dBc/Hz.

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