目前現存之固態硬碟控制器均以單處理器架構為主，並以處理器作為固態硬碟中快閃記憶體管理之核心，此一核心必須執行一個FTL中介軟體(middleware)。由於固態硬碟控制演算法複雜性及整體容量愈趨升高，控制器之效能需求也越來越重要。本論文提出一個多核心固態硬諜控制器架構，搭配一個分散式控制演算法。此架構能夠將FTL的執行分散於各處理器上進而將所需耗費之時間盡可能的隱藏於背景中，因此可大幅提升控制器性能。
為了驗證此架構之效能，本研究實作了一個模擬器，透過搜集實際使用者於Windows XP之存取紀錄並將其輸入於模擬器中執行，可證明雙處理器之控制器可縮短整體存取時間達32%，而4處理器之架構可縮短處理器時間達60%。
最後我們實作了一個FPGA-based系統晶片雛型(prototype)，透過實驗可證明與單處理器之控制器相比，雙處理器之控制器可增進效能1.6倍以上，而4處理器則可增進效能達2.7倍以上。

Most existing architectures of SSD(solid-state disk) controller are single processor to proceed the flash translation layer (FTL) algorithm. However, because of the complexity of system’s functionalities and capacities of flash memory are continuously increased, the design of SSD controller become more delicate than before. In this paper, we propose a multi-core SSD controller architecture. Under this architecture, the latency of processor executing the FTL operations in the background can be mostly eliminated.
To verify the proposed architecture, we implement a simulator and collect the hard drive activity on Windows XP platform. By the experimental results of simulation, we can demonstrate that even with the dual processor based architecture, the system’s access time can be shortened about 32% compared to the single processor based one under usual hard drive accessing convention, and further, the access time can be shortened more than 60% on the system with four processors.
After that, we implement a multi-core based SSD controller prototype on FPGA. By the experimental result on the real system, we can demonstrate that dual processor based controller can improve the system’s performance about 160%, and the controller with four processors can improve the system’s performance about 270%.

[1] Samsung Semiconductor, http://www.samsung.com/global/business/semiconductor/productList.do?fmly_id=672
[2] ASUS website, http://tw.asus.com/
[3] N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, R. Panigrahy, "Design tradeoffs for SSD performance", proceedings of the Usenix Annual Technical Conference, June 2008.
[4] A. Birrell, M. Isard, C. Thacker, T. Wobber, "A design for high-performance flash disks", SIGOPS Oper. Syst. Rev. 41(2), p.88-93 ,2007.
[5] E. Gal , S. Toledo, "Algorithms and data structures for flash memories", ACM Computing Surveys (CSUR), vol.37 no.2, p.138-163, June 2005.
[6] A. Ban 1995. "Flash file system". United States Patent, No. 5,404,485, April.
[7] A. Ban 1999. "Flash file system optimized for page mode flash technologies", United States Patent, 5,937,425, August.
[8] J. Kim, J. M. Kim, S. H. Noh , S. L. Min, Y. Cho, "A space-efficient flash translation layer for compact-flash systems." ,IEEE Transactions on Consumer Electronics vol.48, no. 2, May 2002.
[9] S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park, H. J. Song, "A log buffer-based flash translation layer using fully-associative sector translation", ACM Transactions on Embedded Computing Systems (TECS), vol.6 no.3, July 2007.
[10] S. Y. Park, W. Cheon, Y. Lee, M.-S. Jung, W. Cho, H. Yoon. "A re-configurable FTL (Flash Translation Layer) architecture for NAND flash based applications," in Proc. of International Workshop on Rapid System Prototyping, p.202-208, 2007.
[11] L. P. Chang , T. W. Kuo, " Efficient management for large-scale flash-memory storage systems with resource conservation", ACM Transactions on Storage (TOS), vol.1 no.4, p.381-418, November 2005.
[12] J. K. Kim, H. G. Lee, S. Choi, K. I. Bahng. " A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems", Proceedings of the 8th ACM international conference on Embedded software p.31-40 2008.
[13] J. K. Yoon, E. H. Nam, Y. J. Seong, H. Kim, B. Kim, S. L. Min, Y. Cho, "Chameleon: a high performance Flash/FRAM hybrid solid state disk architecture," IEEE Computer Architecture Letters, 10 Dec 2007.
[14] L. Chang. "Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs," Proc. of Asia and South Pacific Design Automation Conference (ASPDAC), p. 428-433, 2008.
[15] J. U. Kang, J. S. Kim, C. Park, H. Park, J. Lee, "A multi-channel architecture for high-performance NAND flash-based storage system", Journal of Systems Architecture: the EUROMICRO Journal, vol.53 no.9, p.644-658, September, 2007.
[16] L. P. Chang , T. W. Kuo, "An adaptive striping architecture for flash memory storage systems of embedded systems", Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS''02), p.187, September 25-27, 2002.
[17] C. Park, P. Talawar, D. Won, M. J. Jung, J. B. Im, S. Kim, Y. Choi, "A high performance controller for NAND flash-based solid state disk (NSSD)", Non-Volatile Semiconductor Memory Workshop, IEEE NVSMW 2006, p17-20, February 2006.
[18] M. Polte, J. Simsa, G. Gibson. "Comparing performance of solid state devices and mechanical disks", proceedings of the 3rd Petascale Data Storage Workshop held in conjunction with Supercomputing 2008., Austin, TX. November 17, 2008.
[19] C. Dirik, B. Jacob. "The performance of PC solid-state disks (SSDs) as a function of bandwidth, Concurrency, Device Architecture, and System Organization", proceedings of ISCA’09, Austin, Texas, USA, June 20-24, 2009.
[20] D. Narayanan, E. Thereska, A. Donnelly, S. Elnikety, A. Rowstron, "Migrating enterprise storage to SSDs: analysis of tradeoffs", Microsoft Research Ltd. Technical Report MSR-TR-2008-169, November 2008.
[21] S. W. Lee, B. Moon, C. Park, J. M. Kim, S. W. Kim. "A case for flash memory ssd in enterprise database applications, SIGMOD, p.1075-1086, 2008.
[22] W. O.Cesário , D. Lyonnard , G. Nicolescu , Y. Paviot , S. Yoo , A. A.Jerraya , L. Gauthier , M. Diaz-Nava, "Multiprocessor SoC Platforms: A component-based design approach", IEEE Design & Test, vol.19 no.6, p.52-63, November 2002.
[23] A. A. Jerraya , A. Bouchhima , F. Pétrot, "Programming models and HW-SW interfaces abstraction for multi-processor SoC", proceedings of the 43rd annual conference on Design automation, San Francisco, CA, USA, July 24-28, 2006.
[24] T. Kangas , P. Kukkala , H. Orsila , E. Salminen , M. Hännikäinen , T. D. Hämäläinen , J. Riihimäki , K. Kuusilinna, "UML-based multiprocessor SoC design framework, ACM Transactions on Embedded Computing Systems (TECS) ", vol.5 no.2, p.281-320, May 2006.
[25] A. B.T. Hopkins, K. D. McDonald-Maier, "Debug support strategy for systems-on-chips with multiple processor cores", IEEE Transactions on Computer, vol .55, no. 2, February 2006.
[26] Samsung Electronics CO., LTD, K9G8G08U0A Data sheets.
[27] J. L. Hennessy, D. A. Patterson, “Computer Architecture: A Quantitative Approach,” 3rd Ed., Morgan Kaufmann Publishers, Inc., 2003.
[28] DiskMon for windows, http://technet.microsoft.com/en-us/sysinternals/bb896646.aspx
[29] Altera web site, http://www.altera.com/support/software/sof-index.html
[30] Altera, DE2-70 user manual.