在本篇論文中，首先先介紹無接面電晶體的基本操作原理與優點，我們利用二維元件模擬來模擬無接面電晶體元件內部的電位分佈，並且可由電位分佈看出空乏區的寬度，而空乏區的寬度直接影響此元件是否處於導通的狀態，進而可以得知近似的臨限電壓，以及電流對於電壓變化的情況，當元件所外加的閘極電壓達到平帶電壓值時，對於元件本身會產生的反應，並且討論無接面電晶體元件在次臨限區域時，其開關的速度與傳統場效電晶體的比較，同時也使用Poisson’s equation推導無接面電晶體元件二維的空乏區公式，再由空乏區公式推導臨限電壓，並且將此推導結果與我們利用二維元件模擬器得到的模擬結果做比較。

In this thesis, at first we introduce basic operating principles and advantages of the junctionless transistor. We use the two-dimensional device to simulate the potential distribution of the junctionless transistor and then we get the width of the depletion region. The width of the depletion region will decide whether the device is turning on or not, and also we can figure the approximate threshold voltage and the relation between current and voltage. We also discuss the device quality when we apply one voltage source on the gate is more over than the flat-band voltage. And compare the switch speed of the junctionless transistor with a normal transistor, when we operating them in the sub threshold region. Also, we try to derive the equation of the width of the depletion region from Poisson’s equation, and furthermore figure the threshold voltage. At last, we compare the equations with the result we have simulated in two-dimensional device.

[1]D . Grant , “Power semiconductor devices-continuous development ,”Microelectronics Journal, Volume 27, Issues 2-3 , pp. 161-176, March-June1996.
[2]J. T. Park, J. P. Colinge, and C. H. Diaz,“Pi-Gate SOI MOSFET,＂IEEE ElectronDevices Letters, VOL. 22, no. 8,
August 2001.
[3]J. P. Colinge, M. H. Gao, A. Romano, H. Me and C.
Claeys, “Silicon-on-Insulator Gate-All-Around MOS Device,＂IEEE Transaction on Electron Devices, 1990, PP. 137-138.
[4]T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, Y. Ono, Y.Takahashi, and K. Murase,“Ultimately thin double-gate SOI MOSFETs,＂IEEETransaction on Electron Devices, Volume：50 Issue：3 , March 2003,P.830-838.
[5]D. A. Neamen,“Semiconductor physics and devices,＂3rd ed., McGraw-HillCompanies Inc., 2003.
[6]J.-P. Colinge, C.-W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan,I. Ferain, P. Razavi, B. O’Neill, A.
Blake, M. White, A.-M. Kelleher,B. McCarthy, and R.
Murphy, “Nanowire transistors without junctions,”Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Feb. 2010.
[7]S. M. Sze, Physics of Semiconductor Devices: John Wiley & Sons Inc., 2006.
[8]C.-W. Lee, A. N. Nazarov, I. Ferain, N. Dehdashti
Akhavan, R. Yan,P. Razavi, R. Yu, R. T. Doria, and J.-P. Colinge, “Low subthreshold slopein junctionless
Multigate transistors,” Appl. Phys. Lett., vol. 96, no. 10,p. 102 106, Feb. 2010.
[9]R. M. Y. Ng, T. Wang, F. Liu, X. Zuo, J. He, and M. Chan, “Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation,” IEEE Electron Device Lett., vol. 30,no. 5, pp. 520–522, May 2009.
[10]J. Colinge, “Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, no. 3,pp. 718–723,Mar. 1990.
[11]Juan P. Duarte, Sung-Jin Choi, Dong-Il Moon, and Yang-Kyu Choi, “Simple Analytical Bulk Current Model for Long-Channel Double-Gate JunctionlessTransistors,” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 6, pp. 704-706 JUNE 2011