| 研究生: |
應子翔 Tzu-Hsiang Ying |
|---|---|
| 論文名稱: |
二維半導體元件功率與溫度分佈之模擬 Power and Temperature Distributionby 2-D Semiconductor Device Simulation |
| 指導教授: |
蔡曜聰
Yao-Tsung Tsai |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 畢業學年度: | 97 |
| 語文別: | 中文 |
| 論文頁數: | 51 |
| 中文關鍵詞: | 功率分佈 、溫度分佈 |
| 外文關鍵詞: | power distribution, temperature distribution |
| 相關次數: | 點閱:6 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
摘 要
在本篇論文中,我們使用Poisson’s equation 以及 electron continuity equation
和hole continuity equation設計出包含一維及二維的等效電路模型。藉由此等效電路模型所建構的模擬器,可幫助我們探討元件內部載子復合(recombination)的情形,並將其應用在各式元件內部功率分佈(power distribution)的討論,以及探究隨著功率消耗(power dissipation)而來的熱效應。我們以各式半導體元件為論文的核心,首先是一維及二維的二極體(diode),探討基本位勢曲線及其功率分佈狀況,
並討論在不同摻雜情況下其功率分佈的差異。功率分佈對於半導體元件分析及設
計上,扮演著相當重要的角色。因此,在與二維二極體相同的基礎上,我們也探
討了BJT(Bipolar Junction Transistor ),觀察其在不同偏壓大小及調整摻雜的情況
下功率分佈的差異。最後,由於載子復合產生的功率會發生消耗的情況,使得元
件內部溫度提高,我們利用二維等效電路模型模擬出以功率作為熱源,觀察元件內部發燙生熱的情況,探討各式不同元件在導通時溫度的分佈情況,可作為元件可靠度的參考。
Abstract
In this paper, we use Poisson’s equation and continuity equations to design the 1-D and 2-D device simulators. The device simulator can help us to simulate the carrier recombination of the device and discuss power distribution in the device. It also can be used to study heat effect by power dissipation. First, we study potential and power distribution. We also discuss the power distribution in a pn diode with different doping. Power distribution plays an important role in device design. Therefore, based on 2-D PN junction , we observe BJT’s power distribution in different bias and doping. Finally, because power dissipation increase the temperature in device, we use 2-D temperature simulator to simulate temperature distribution in 2-D devices. This simulator can be a useful tool for 2-D device analysis.
Reference
[1] C. C. Chang, S. J. Li, and Y. T. Tsai, “Device-partition method using Equivalent Circuit Model in Two-dimensional Device Simulation,” International Journal of Numerical Modelling, vol. 18, pp. 203- 219, 2005.
[2] Y. T. Tsai, C. Y. Lee, and M. K. Tsai “Levelized incomplete LU method and its application to semiconductor device simulation,” Solid-state Electronics, Vol. 44, pp. 1069-1075, 2000.
[3] C. C. Chang, J. F. Dai, and Y. T. Tsai, “Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation, “ International Journal of Numerical modeling: Electronic Networks, Devices, and Fields, vol. 16, pp. 81-94, 2003.
[4] J. F. Dai, C. C. Chang, and Y. T. Tsai, “Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation, “Solid-state Electronics, vol. 48, pp.1181-1188, 2004.
[5] J. F. Dai, C. C. Chang, J. W. Lee, S. J. Li, and Y. T. Tsai, “Simplified equivalent-circuit modeling for decoupled and partial decoupled methods in semiconductor device simulation, “International Journal of Numerical modeling: Electronic Networks, Devices, and Fields, vol. 17, pp. 421-432, 2004.
[6] A. Schutz, S. Selberherr, and H. W. Potzl, “ A two-dimensional model of the avalanche effect in MOS transistors,” Solid-state Electronics, vol. 25, pp.177-183, 1982.
[7] C. C. Chang, S. J. Li, and Y. T. Tsai, “An Equivalent-circuit Modeling on Vertical and Horizontal Integrations for MOS Flat-band Voltage Simulation,” International Journal of Numerical Modelling , vol. 19, pp. 289- 300, 2006.
[8]D.A. Neamen, “Semiconductor Physics and Devices”, Chapter8, McGRAW-HILL,2003.
[9] A. S. Sedra/K. C. Smith, “MICROELECTRONIC CIRCUITS”, Chapter 5,Oxford University Press,2004.
[10] 出自:http://www.iue.tuwien.ac.at/phd/grasser/node34.html