在製造晶片的過程中，電路佈局可能因為微塵粒子或是設計錯誤的影響
而導致晶片運作結果與預期不同。若修正設計後再重新執行設計流程，將延
後產品上市時間。因此，聚焦離子束(Focused Ion Beam, FIB) 技術被用來
矽後除錯與直接修正電路佈局，替代重複的設計流程，使產品上市時間不受
影響。
隨著製程的演進，積體電路元件尺寸逐漸縮小，電路繞線密度也隨之提
升。但是，聚焦離子束的技術卻無法跟上製程的演進，導致先進製程的電路
難以利用聚焦離子束進行探測或電路編輯，嚴重限制電路的測試與除錯。實
施聚焦離子束程序時所影響的範圍，遠大於先進製程的線寬與線距，若繞線
密度過高，在實施聚焦離子束程序時將影響到多條鄰近的訊號線。以90奈米
製程的電路為例，只有百分之三十的訊號線有足夠的空間可以實施聚焦離子
束程序。
本研究旨在細部繞線階段提升聚焦離子束能見度。我們提出繞線格點上
的三種聚焦離子束狀態(仰視狀態、俯視狀態和環視狀態) 及其代價，並修
改迷宮繞線之波傳遞方法，使得每條訊號線找到一條有足夠空間可以實施聚
焦離子束程序的最短路徑。實驗結果顯示，我們所提出的方法可以達到百分
之百的可繞度，並且將可以實施聚焦離子束程序的訊號線數量最大化。

In the process of manufacturing a chip, a circuit layout which is affected
by particles or design errors may cause that the chip operation differs with the
desired one. As a result, post-silicon debug becomes a critical and necessary
step in the current design flow. Therefore, instead of the iterative design
process, focused ion beam (FIB) technology is used to improve the time to
market by directly correcting the circuit layout.
As the manufacturing process evolves, the size of ICs is gradually reduced,
and the wire density of a circuit increases. However, FIB technology cannot
keep up with the evolution of the manufacturing process. Therefore, the FIB
cannot be easily used in probing or circuit editing, incurring the limitations of
testing and debugging. Since the influence of FIB is much larger than the line
spacing and width, the FIB process will affect several adjacent signal lines if
the wire density is too high. For example, only 30% signal lines for a circuit
using the 90-nm process can apply FIB.
The purpose of this thesis is to improve the FIB observable rate in the
detailed routing stage. We propose three FIB states (lookup, lookdown, and
lookpin) with their costs in the routing grid, and modify the wave propagation
stage in the maze routing to find a shortest path which has enough space to
process FIB for each net. Experimental results show that the proposed method
can achieve 100% routability with maximizing the number of signal lines which
can apply FIB.

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