在SoC(system-on-chip)的時代，混合訊號電路將是IC設計的趨勢。隨著電路設計複雜度的增加，模擬所花費的時間也隨著增加，尤其是在混合電路的模擬上。若要減少電路設計時所花費的時間，則模擬的時間必須要加快。在傳統的電晶體層級(transistor level)上模擬，會因為數位電路的複雜度太高，所以無法有效的提昇模擬速度，因此提昇抽象層次將是主要的方法。從前混合訊號電路在共同模擬(co-simulation)上主要的瓶頸在於Spice無法在行為層級(behavioral level)上模擬。目前可以使用Verilog-A來描寫類比電路的行為模型(behavioral model)，因此混合電路的模擬提升到行為層級，模擬的時間將大幅的減少。Verilog-A行為模型是利用一連串的數學式子來描寫電路的行為模式，也因此模型內的參數值將影響行為模型的準確度。在此篇論文我們使用鎖相迴路當作研究的電路，並建立了一套標準的參數粹取流程，可以利用鎖相迴路的開迴路轉換函數，找出我們所需要的參數值，使我們的行為模型所模擬出來之波形與Spice的模擬波形很相似，並可以適用於各式各樣的鎖相迴路，而不一定需要使用者手動填入。

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