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研究生： 黃品玄
Pin-Hsun Huang
論文名稱： 可規劃式維特比解碼器之設計與實現
Design and Implementation of a Reconfigurable Viterbi Decoder
指導教授： 蔡宗漢
Tsung-Han Tsai
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 89
語文別： 中文
論文頁數： 68
中文關鍵詞： 迴旋碼 、維特比演算法 、可規劃式
外文關鍵詞： convolutional code, viterbi algorithm, reconfigurable
相關次數： 點閱：12  下載：0 
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    • 在本論文中，我們著重於可規劃式維特比解碼器的發展。我們先介紹我們所提出的可規劃式維特比解碼器。在設計的過程中，我們會探討實現上的要素且選定我們所要採用的架構；接著我們以Matlab程式驗證整個解碼運作的過程，並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後，我們以Altera FLEX 10K200E來實現我們的設計。


    In this thesis, we focus on the development of the Reconfigurable Viterbi Decoder (RVD). Hence, we will introduce the concept of RVD. In the realization of RVD, we discuss the implementation issues and the proposed architecture firstly. Then, the decoding process is simulated by using Matlab and verified by Verilog HDL. Finally, the decoder is realized by the FPGA device.

    CHAPTER 1INTRODUCTION1 1.1OVERVIEW OF ECC IN THE COMMUNICATION SYSTEM1 1.2CONVOLUTIONAL CODES AND VITERBI ALGORITHM2 1.3MOTIVATION AND OBJECTIVE3 1.4THESIS ORGANIZATION4 CHAPTER 2CONVOLUTIONAL CODE AND THE VITERBI ALGORITHMS5 2.1CONVOLUTIONAL CODES5 2.1.1Definition of a Convolutional Code6 2.1.2Trellis Diagram of a Convolutional Code9 2.1.3Decoding the Convolutional codes11 2.2THE VITERBI ALGORITHM12 2.2.1Definition of Viterbi algorithm13 2.2.2An example of Viterbi Decoding15 2.2.3Basic Processing Units of Viterbi Decoders18 CHAPTER 3RECONFIGURABLE VITERBI DECODERS20 3.1FIXED STATE NUMBER TRELLIS DIAGRAM AND FIXED STATE RECONFIGURABLE VITERBI DECODER20 3.2RECONFIGURABLE VITERBI DECODER27 3.2.1Floating State Reconfigurable Viterbi Decoding27 3.2.2Proof of the Floating State Reconfigurable Viterbi Decoding29 3.3METHODOLOGY OF DESIGNING A RVD35 CHAPTER 4IMPLEMENTATION ISSUES OF OUR PROPOSED RVD37 4.1IMPLEMENTATION ISSUES OF VITERBI DECODER37 4.1.1Implementation Issues of BMU37 4.1.2Implementation Issues of ACSU40 4.1.3Implementation Issues of SMU44 4.2THE STRUCTURE OF OUR PROPOSED RVD45 CHAPTER 5FPGA IMPLEMENTATIONS AND VERIFICATION50 5.1ALTERA FPGA50 5.1.1Altera FLEX10K200E51 5.1.2Altera FPGA Design Flow52 5.2IMPLEMENTATIONS OF THE PROPOSED RVD53 5.2.1Matlab Simulation Result53 5.2.2FPGA Realization57 CHAPTER 6CONCLUSION65 6.1SUMMARY65 6.2FUTURE WORKS65 REFERENCE67

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