在此主要的研究目標是載波回復電路的設計。在許多的數位通訊系統中，載波的同步化是很主要的課題，以一個有效頻寬的調變而言，系統對於相位雜訊是非常敏感的，同時也需要一個非常窄的回路頻寬以得到最小的相位雜訊。不過由於射頻震盪器的不確定性以及通道的影響，造成在系統上接收端最大仍有 100 kHz 的頻率誤差。然而為了維持相位，當有頻率漂移的情況下，載波回復電路仍可以鎖住相位並達到最小的相位雜訊。
由於在 ATSC的規範中多加一個1.25 DC 值的嚮導信號 (Pilot signal) 到資料中，整個調變方式就變成 載波傳送 (Transmitted Carrier)。載波傳送 的好處在於它可以用比 載波壓抑 (Suppressed Carrier) 用更少的硬體來實現同時減少設計的困難度，不過缺點就是要浪費更多的傳送能量。傳統上可以利用 Citta''s loop 來完成載波同步化。
在提出的新架構中，利用了 領先/落後偵測 和 差值/累加鎖頻迴路 等全數位的觀念將它應用在整個系統中來同步化載波訊號。不但整個系統是操作在一階的鎖相迴路之中，沒有不穩定的情況產生。同時只需要一個很簡單的一階 IIR 低通濾波器便可以去除掉大部分的雜訊，使得相位偵測的錯誤機會可以降低到 25%，因此晶片面積更是大幅降低。
我們透過 C 和 Verilog 的模擬驗證其可行性，並且利用 TSMC 0.35μm 製程和CIC 提供的唯讀記憶體來作實現，整個電路只用3000多個邏輯閘(不包括唯讀記憶體)，整個晶片面積為 1000μm X 800μm不但大大減少硬體複雜度並且佈局的面積也很小。同時載波回復電路可將頻率誤差由 拉至 。在穩定狀態時，最大相位雜訊約是 6 度，相位標準差為 1.5 度。

In this paper, a carrier recovery circuit for the ATSC HDTV has been proposed and implemented. It uses the Sigma-Delta Modulation to achieve large pull-in range and small steady state variation simultaneously. The proposed architecture has the following distinguishing features. First, it uses only the lead-lag decision for the carrier recovery instead of the phase difference information for the PLL to minimize the hardware complexity. Second, it takes the 1st order PLL approach for the stability and phase jitter considerations. Third, the Sigma-Delta modulation helps achieve large pull-in range and small steady variation. The architecture and the logic design have been verified using C Language and Verilog simulation respectively. The chip has been designed implemented using TSMC 0.35μm technology. The gate count of 3000 reconfirms the simplicity of the architecture.

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