使用三五族以及矽基製程實現之高速高線性度高解析度追蹤保持放大器

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研究生：	林俞安 Yu-An Lin
論文名稱：	使用三五族以及矽基製程實現之高速高線性度高解析度追蹤保持放大器 Design and Analysis of High Speed High Linearity High Resolutoin Track-and-Hold Amplifier in III-V andSilicon-Based Processes
指導教授：	張鴻埜 Hong-Yeh Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	中文
論文頁數：	161
中文關鍵詞：	追蹤保持放大器、毫米波積體電路、混合訊號積體電路
外文關鍵詞：	Track-an-Hold Amplifier, Microwave Integrated Circuit, Mixed-signal Integrated Circuit
相關次數：	點閱：8 下載：0
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本論文主要探討應用於高速資料轉換系統微波及毫米波頻段高線性度追蹤與保持放大器，所提出的設計、研究以及理論計算分析結果將以實驗結果來做驗證。高速追蹤保持放大器的詳細介紹與設計考量將在第二章呈現。
第三章為使用砷化鎵增強型高速電子遷移率電晶體製程所實現之具有直流到82.4 GHz的寬頻放大器，所提出的寬頻放大器使用共源級架構搭配頻寬提升技術來做設計，其頻率響應、輸入阻抗以及輸出阻抗將加以分析以獲得最佳的設計方法，所提出的寬頻放大器架構具有328 GHz增益頻寬乘積和0.7 × 1毫米平方的電路面積，此放大器使用資料量為40 Gbps偽隨機二進位數列量測方式來驗證所提出的設計方法，所提出的寬頻放大器架構由於其良好的電路特性，適合應用在高資料傳遞系統中。
第四章為使用0.18微米矽鍺製程所實現的高速寬頻高線性的追蹤保持放大器，所提出的放大器使用開關射級隨偶器追蹤保持電路與疊接架構實現高解析度類比數位轉換，並且修改傳統的達靈頓寬頻電路，搭配電感提升技術以大幅提升整體的輸入頻寬，所提出的追蹤保持放大器架構具有94.3毫瓦特直流功耗、直流到27 GHz 3-dB輸入頻寬、45 dBc無失真動態範圍、-43.9 dB的總諧波失真，由於所提出的電路具有良好的電路特性，在使用多相位的時脈取樣下，將可實現超高速取樣速率。
第五章為使用砷化鎵增強型高速電子遷移率電晶體所實現的追蹤保持放大器，根據文獻，此電路為第一個使用砷化鎵增強型高速電子遷移率電晶體所設計的追蹤保持放大器，所提出的架構修改傳統開關源級隨偶器追蹤保持電路以增加整體電路的取樣率以及解析度，並且大幅減小開關時脈所造成的動態非線性度，搭配使用差動架構，輸出偶模非線性失真可大幅度的下降，追蹤保持放大器的無失真動態範圍以及總諧波失真亦可大幅度的下降，輸入以及輸出緩衝級使用分佈式放大器以及源級隨偶器架構去實現高輸入與輸出反射損耗，所提出的追蹤保持放大器架構具有直流到16 GHz的頻寬、46 dBc的無失真動態範圍以及13.5 GS/s取樣率。
第六章使用40奈米互補式金屬氧化物半導體電晶體製程實現高速以及高動態範圍的追蹤保持放大器，此電路使用差動消除器來做設計，實現接近無限大的保持模態隔離度，使用差動消除器架構亦改善了整體電路的線性度以及保持模態改變率，當輸入50 GS/s取樣率和5 GHz輸入信號時，模擬無失真動態範圍以及總諧波失真可分別達到47 dBc以及−44.6 dBc，所提出的追蹤保持放大器架構實現了60 GHz的輸入頻寬以及396 毫瓦特的直流功耗，此電路的量測結果和重新模擬結果將搭配電路布局電路技巧來做詳細的分析，由於此電路的高速、高線性度以及低直流功號的電路特性，所提出的追蹤保持放大器架構將可拿來與其他使用先進製程所設計的電路比較。
最後，總結了本論文所提出電路設計架構，並且提出未來設計方向以達到更高速、更寬頻、更好的電路線性度。

Several microwave and millimeter wave (MMW) high linearity track-and-hold amplifiers (THAs) for high speed data conversion systems are presented in this dissertation. Design, investigation and analysis of THAs shown in this dissertation are verified by the experimental results. The introduction and design considerations of THA are demonstrated in Chapter 2 in details.
A compact DC-to-82.4-GHz broadband amplifier using 0.15 μm　GaAs E-mode PHEMT process is demonstrated in Chapter 3. The amplifier is implemented in common-source (CS) configuration with bandwidth extension technique. The frequency response and input and output impedances of the amplifier are investigated to obtain the design methodology. The amplifier exhibits a high gain-bandwidth product (GBP) of 328 GHz with a chip size of 0.7 × 1 mm2. Moreover, the amplifier is evaluated using pseudorandom bit stream (PRBS) signal with a data rate up to 40 Gbps. The proposed amplifier has potential for the high-speed data rate transmission due to its superior performance.
A broadband high-speed high-linearity THA is presented in Chapter 4 using 0.18 μm SiGe process. A switched emitter follower (SEF) track-and-hold (T/H) stage with cascode stage is adopted to achieve high resolution for analog-to-digital conversion. A modified Darlington amplifier with peaking technique is used to enhance the input bandwidth. With a DC power consumption of 94.3 mW, the proposed THA demonstrates a 3-dB input bandwidth from DC to 27 GHz, a maximum spurious-free dynamic range (SFDR) of 45 dBc, and a minimum total harmonic distortion (THD) of -43.9 dBc. The proposed circuit has potential for high-speed sampling rate as using time-interleaved architecture due to its superior performance.
Chapter 5 presents the design and analysis of the first GaAs-based THA. The conventional switched source follower (SSF) T/H stage is modified to enhance the sampling rate and resolution. The modified SSF T/H stage is designed and investigated to further reduce input-dependent timing jitter existed in the conventional SSF. Moreover, by using the differential topology, the even mode harmonic distortion is successfully suppressed and the SFDR and THD are improved. With the distributed amplifier (DA)-base input buffer and source follower-based output buffer, the proposed THA features a bandwidth from DC to 16 GHz, a maximum SFDR of 46 dBc and a maximum sampling rate of 13.5 GS/s.
In Chapter 6, a 40 nm CMOS high speed high dynamic range THA is proposed using a differential feed-through cancellation technique. The simulated isolation is approximate to infinity over the input bandwidth as the THA is operated in the hold mode. The linearity and droop rate are enhanced due to the feed-through cancellation. With a sampling rate of 50 GS/s and an input frequency of 5 GHz, the SFDR and THD are better than 47.6 dBc and −44 dBc, respectively. The simulated input bandwidth is up to 60 GHz, and the total DC power consumption is 396 mW. The measured results and resimulated results with several significant layout considerations are detailed as well. The proposed THA can be suitable for the handheld electronic applications, and the circuit performance can be compared to the advanced silicon-based THAs due to its high speed, good linearity, and low DC power.
Lastly, the future work and the conclusions are addressed in Chapter 7.

摘要.................................................................................................................................I
Abstract ........................................................................................................................III
致謝 ...............................................................................................................................V
Contents  ....................................................................................................................VIII
List of Figures    XII
List of Tables    XIX
Chapter 1 Introduction    1
1    Motivation    1
2    Literatures Survey    4
3    Contributions    8
4    Dissertation Organization    10
Chapter 2 Introduction of THA    12
1    Introduction    12
2    Specifications Discussion    16
2.1    Linearity    16
2.2    Operated Speed    20
2.3    Resolution    24
2.4    Dynamic Range    28
2.5    DC Power Consumption    28
2.6    Chip Area    29
3    General Topologies of T/H Stage    30
3.1 Switched Capacitor (SC)    30
3.2 Switched Source Follower (SSF) / Switched Emitter Follower (SEF)    32
3.3 Diode switch    33
4    Measurement Setup    35
Chapter 3 A DC-to-82.4-GHz Broadband Amplifier Using Bandwidth Extension Technique in 0.15 μm PHEMT Process    37
1    Introduction of GaAs Process    38
2    Introduction of Low Pass Response    39
3    Performance Metrics    41
3.1    Gain-Bandwidth Product    41
3.2    Return Loss    42
3.3    1-dB Compression Point    43
3.4    Third-Order Intercept Point    44
3.5    Noise Figure    45
3.6    DC Power Consumption    46
3.7    Circuit Area    47
4    Conventional Broadband Amplifier    48
4.1    Peaking Technique    48
4.2    Darlington Pair    52
4.3    Distributed Technique    53
5    Analysis of Negative Feedback    57
6    Experimental Results    64
6.1    On-Wafer Measurement    64
6.2    Summary    71
7    Conclusion    73
Chapter 4 A 27-GHz 45-dBc SFDR Track-and-Hold Amplifier using Modified Darlington Amplifier and Casoded SEF in 0.18 μm SiGe Process    74
1    Introduction of SiGe BiCMOS Process    75
2    Cascoded Switched Emitter Follower Track-and-Hold Stage    76
3    Modified Darlington-Based Input Buffer    82
4    Source Follower Output Buffer    84
5    The Modified Darlington and Cascoded SEF T/H Stage THA    86
6    Experimental Results    89
7     Conclusion    92
Chapter 5    Design of Low Distortion Track-and-Hold Amplifier Using Dynamic Nonlinearity Degradation Topology in 0.15 μm GaAs Process...............93
1 Modified Switched Source Follower Track-and-Hold Stage    94
2    Distributed Amplifier-Based Input Buffer    99
3    The DA-Based Input Buffer and Modified SSF T/H Stage THA    101
4    Experimental Results    103
5    Conclusion    106
Chapter 6    A 60-GHz Bandwidth 50-GS/s Track-and-Hold Amplifier in 40 nm CMOS Process using Differential Cancellation Technique..................................107
1 Modified Switched Capacitor Track-and-Hold Stage    108
2 Active Inductive Peaking-Based Input & Output Buffers    114
3 The Modified SC T/H Stage and CS Amplifier Buffers THA    117
4 Simulated Results    119
5    Measured and Resimulated Results    122
5.1    Measured Results    122
5.2    Analysis of Layout Considerations    125
5.3    Performance Summary    126
6 Conclusion    127
Chapter 7     Conclution and Future Work....................................................................128
Reference    131
Publication List    137


                                

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