隨著積體電路製程的演進，混合訊號系統的電路設計變得越來越複雜，如何加速類比與數位訊號的模擬速度，是驗證系統晶片時極為重要的環節。以硬體描述語言建立類比電路的行為模型，可以有效率的進行混合訊號系統的驗證。如果能透過自動化的方式將每個類比電路轉換成對應的行為模型，便可以大幅降低類比部分的模擬時間，本論文發展出一套有效率的電路架構分析流程，可以自動的從電路特徵或是接線關係中萃取出混合訊號電路中的構成區塊。透過獨特的編碼方式可以準確的將Netlist電路中的數位和類比模型辨識出來並且替換成資料庫中所對應的行為模型。然而，在前人的論文中，可能會出現架構重疊的問題，因此本論文則透過機器學習模型，依據電路模擬結果和資料庫的相似度，準確地決定出電路所屬的架構，如實驗結果所示，可以有效提升辨識結果的準確性，並且可以減少額外的系統驗證工作。

The design of analog/mixed-signal (AMS) integrated circuits is getting complex as technology advances. Speeding up AMS simulation becomes a key to solve the system verification issues for SOC designs. Building their behavioral models for analog circuit blocks by hardware description language is an efficient approach for verifying AMS systems. If each analog circuit can be transformed into their corresponding behavioral models automatically, the simulation time for the analog part can be greatly reduced. In this thesis, we have developed an efficient structure analysis flow that can extract the building blocks, no matter it is an analog block or digital block, in a mixed-signal design automatically based on given circuit specifications and netlist. Using a special encoding scheme, the digital and analog blocks in the netlist can be identified quickly and replaced by the behavior models built in the library. However, in previous works, the identified blocks may have overlap issues. In this thesis, we use machine learning model to help users determine the correct structure that each device belongs to based on the similarity of real simulation behaviors. As shown in the experiments, the efficiency and accuracy of the identification results can be improved to reduce the extra efforts for system verification.

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