超大型積體電路設計日益複雜，加上奈米效應使得晶片與封裝的設計變得更加困難，因此電子設計自動化產品也必需不斷的進步以符合時代的需求。由於市場需求，電路需擁有較高的效能與較低的供應電壓等特性，且因所需的輸入/輸出埠不斷增加造成封裝設計上困難度不斷的增加。在此論文中，我們提出了幾個新的佈局規劃與配置方法。這些方法不只可以解決電源雜訊上的問題，還可以考慮封裝設計以及堆疊晶片的設計問題。
關於電源雜訊中的同時性邏輯轉換雜訊問題方面，我們採用了一個二階式技術:佈局規劃與電容插入。首先利用佈局規劃的方法盡可能抑制雜訊，之後再藉由去耦合電容插入的方法，來改善雜訊問題。因佈局規劃與電容插入的方法均有考慮到整體面積的問題，因此最後因為改善雜訊而付出的面積代價是非常小的。關於電源雜訊中的電壓降雜訊與封裝設計方面，我們採用了一個推算輸入/輸出埠排序的方法來解決此一問題，主要是因為輸入/輸出埠的排序會影響到晶片核心的電壓降雜訊與封裝繞線複雜度。雖然現今的輸入/輸出埠數量非常的大，但我們的推算方法只需要花費O(n)的時間就可推算出最適的位置。另外，堆疊設計是最能有效提供高效能晶片的設計方法，在論文中我們提出了一個分割方法來有效配置輸入/輸出埠的位置，且此一方法能同時考量連接元件數量。最後再用佈局規劃方法來改善對於最後整體晶片面積的影響。

In modern VLSI deigns, manufacturing issues have complicated the designs of chips as well as packages. Moreover, due to the requirement of the market, modern circuits have higher functionality, lower supply voltage and more I/Os. These conditions increase complexity of chip designs. In this dissertation, we present some I/O plan and floorplan methods to solve these problems. They cannot only be applied to mitigate the power supply noise in the core, but also can consider the package designs, and stacking IC designs.
For the simultaneous switching noise, our method adopts a two-stage technique of the floorplan followed by the decoupling capacitance (decap) insertion. In the floorplan, the area and noise are evaluated to find a noise-driven floorplanning result. Then, we use a noise-driven decap planning approach to inserting minimal decaps into a floorplan. For IR-drop and the packages issues, we adopt a finger/pad assignment method to solve these problems. Our finger/pad assignment is a two-step method: we first solve the package design problem, then try to minimize IR-drop by switching finger/pad locations. In addition, since stacking IC is promising to the development of a high-performance IC, in this dissertation, we propose a partition approach to minimizing the 3D-vias and balancing the I/O number for each tier in stacking IC. Finally, we perform a floorplanning to show the importance of the aspect-ratio factor in stacking IC.

[1] International Technology Roadmap for Semiconductors. http://public.itrs.net/
[2] M. Ieong, K.W. Guarini, V. Chan, K. Bernstein, R. Joshi, J. Kedzierski and W. Haensch, "Three Dimensional CMOS Devices and Integrated Circuits," IEEE Custom Integrated Circuits Conference, pp. 207-213, September 2003
[3] S.F. Al-sarawi, D. Abbott and P.D. Franzon, "A Review of 3-D Packaging Technology," IEEE Transaction on Components, Packaging and Manufacturing, vol. 21, no. 1, pp. 2-14, February 1998
[4] A. Klumpp, R. Merkel, R. Wieland and P. Ramm, "Chip-to-wafer Stacking Technology for 3d System Integration," IEEE Electronic Components and Technology Conference, pp. 1080-1083, May 2003
[5] S.K. Lim, "Physical Design for 3d System on Package," IEEE Design and Test of Computer, vol. 22, no. 6, pp. 532-539, November 2005
[6] R. Tummala, "Packaging: Past, Present and Future," IEEE Electronic Packaging Technology, pp. 3-7, September 2005
[7] T. Fukushima, Y. Yamada, H. Kikuchi and M. Koyanagi, "New Three-dimensional Integration Technology Using Self-assembly Technique," IEEE International Electron Devices Meeting, pp. 348-351, December 2005
[8] J. Burns, B. Aull, C. Chen, C.-L. Chen, C. Keast, J. Knecht, V. Suntharalingam, K. Warner, P. Wyatt and D.-R. Yost, "A Wafer-scale 3-d Circuit Integration Technology," IEEE Electron Devices, vol. 53, no. 10, pp. 2507-2516, October 2006
[9] J. Feng, Y. Liu, P. Griffin and J. Plummer, "Integration of Germanium-on- insulator and Silicon Mosfets on a Silicon Substrate," IEEE Electron Device Letters, vol. 27, no. 11, pp. 911-913, June 2006
[10] W.-C. Lo, Y.-H. Chen, J.-D. Ko, T.-Y. Kuo, Y.-C. Shih and S.-T. Lu, "An Innovative Chip-to-wafer and Wafer-to-wafer Stacking," IEEE Electronic Components and Technology, pp. 409-414, June 2006
[11] T. Mitsuhashi and E.S. Kuh, "Power and Ground Network Topology Optimization for Cell Based VLSIs," IEEE/ACM Design Automation Conference, pp. 524-529, June 1992
[12] X.D.S. Tan and C.J.R. Shi, "Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling," IEEE/ACM Design Automation Conference, pp. 550-554, February 2001
[13] H. Su, K. Gala and S. Sapatnekar, "Fast Analysis and Optimization of Power/Ground Networks," IEEE International Conference on Computer-Aided Design, pp. 477-480, November 2000
[14] R. Dutta and Malgorzata Marek-Sadowska, "Automatic Sizing of Power/Ground (P/G) Networks in VLSI," IEEE/ACM Design Automation Conference, pp. 783-786, June 1989
[15] C.Y. Yeh and Malgorzata Marek-Sadowska, "Timing-Aware Power Noise Reduction in Layout," IEEE/ACM International Conference on Computer-Aided Design, pp. 627-634, November 2005
[16] J.-T. Yan, K.-P. Lin and Y.-H. Chen, "Decoupling Capacitance Allocation in Noise-aware Floorplanning Based on DBL Representation," Internationl Symposium on Circuits and Systems, pp. 23-26, May 2005
[17] S. Zhao, K. Roy and C.K. Koh, "Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplan," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 81-92, January 2002
[18] H.-M. Chen, L.-D. Huang, I Min. Liu and D.F. Wong, "Simultaneous Power Supply Planning and Noise Avoidance in Floorplan Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 578-587, April 2005
[19] A. B. Kahng, B. Liu and S. X.-D. Tan, "Efficient Decoupling Capacitor Planning Via Convex Programming Methods," International Symposium on Physical Design, pp. 102-107, April 2006
[20] H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "Rectangle-Packing Based Module Placement," IEEE International Conference on Computer Design, pp. 472-479, November 1995
[21] Y.-C. Chang, Y.-W. Chang, G.-M. Wu and S.-W. Wu, "B*-trees: A new Representation for Nonslicing Floorplans," IEEE/ACM Design Automation Conference, pp. 258-263, June 2000
[22] P.-N. Guo, C.-K. Chen and T. Yoshimura, "An O-tree Representation of Nonslicing Floorplan and Its Application," IEEE/ACM Design Automation Conference, pp. 268-273, June 1999
[23] J.-M. Lin and Y.-W. Chang, "TCG: A Transitive Closure Graph-Based Representation for General Floorplans," IEEE/ACM Design Automation Conference, pp. 764-769, February 2001
[24] X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong and C.K. Cheng, "Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan," IEEE/ACM Design Automation Conference, pp. 764-769, November 2001
[25] S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220, pp. 671-680, May 1983
[26] K. Sheth, E. Sarto and J. McGrath, "The Importance of Adopting a Package-Aware Chip Design Flow," IEEE/ACM Design Automation Conference, pp. 853-856, June 2006
[27] M.-F. Yu and W.-M. Dai, "Single-layer Fanout Routing and Routability Analysis for Ball Grid Array," IEEE International Conference on Computer Design, pp. 581-586, October 1995
[28] Y. Kubo and A. Takahashi, "Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 725-733, April 2006
[29] T. Miyoshi, S. Wakabayashi, T. Koide and N. Yoshida, "An MCM Routing Algorithm Considering Crosstalk," Internationl Symposium on Circuits and Systems, pp. 212-214, May 1995
[30] M.M. Ozdal, D.F. Wong and P.S. Honsinger, "Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 84-95, January 2008
[31] N.L. Koren, "Pin Assignment in Automated Printed Circuit Board Desing," IEEE/ACM Design Automation Conference, pp. 72-79, June 1972
[32] L. Mory-Rauch, "Pin Assignment on Printed Circuit Board Desing in Design Automation," IEEE/ACM Design Automation Conference, pp. 70-73, June 1978
[33] T.D. Am, M. Tanaka and Y. Nakagiri, "An Approach to Topological Pin Assignment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 3, no. 3, pp. 250-255, July 1984
[34] J. Singh and S.S. Sapatnekar, "Congestion-Aware Topology Optimization of Structured Power/Ground Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 5, pp. 683-695, May 2005
[35] J. Fu, Z. Luo, X. Hong, Y. Cai, S. D. Tan and Z. Pan, "VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Currents," IEEE Asia and South Pacific Design Automation Conference, pp. 735-738, January 2005
[36] A. Dubey, "P/G Pad Placement Optimization: Problem Formulation for Best IR Drop," International Symposium on Quality Electronic Design, pp. 340-345, March 2005
[37] C.-H. Lu, H.-M. Chen, C.-N. Liu and W.-Y. Shih, "Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design," IEEE/ACM Conference of Design, Automation, and Test in Europe, pp. 845-850, April 2009
[38] Y. Zhong and M. D. F. Wong, "Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid," IEEE Asia and South Pacific Design Automation Conference, pp. 768-773, January 2007
[39] Y. Zhong and M. D. F. Wong, "Fast Algorithms for IR Drop Analysis in Large Power Grid," IEEE/ACM International Conference on Computer-Aided Design, pp. 351-357, October 2005
[40] K. Shakeri and J.D. Meindl "Compact Physical IR-Drop Models for Chip/Package Co-Design of Gigascale Integration(GSI)," IEEE Transactions of Electron Devices, vol. 52, no. 6, pp. 1087-1096, June 2005
[41] J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner and P. Wyatt, "Three-dimensional Integrated Circuits for Low-power, High-bandwidth Systems on a Chip," Internation Solid State Circuits Conference, pp. 268-269, February 2001
[42] S. Das, A. Chandrakasan and R. Reif, "Technology, Performance, and Computer-aided Design of Three-dimensional Integrated Circuits," IEEE/ACM International Symposium on Physical Design, pp. 108-115, April 2004
[43] S. Das, A. Fan and K.-N. Chen, "Design Tools for 3-d integrated Circuits," IEEE Asia and South Pacific Design Automation Conference, pp. 53-56, January 2003
[44] S. Das, A. Fan and K.-N. Chen, "Three-dimensional Integrated Circuits: Performance, Design Methodology, and Cad Tools," IEEE Computer Society Annual Symposium on VLSI, pp. 13-18, February 2003
[45] P.D. Franzon, W.R. Davis, M.B. Steer, S.Lipa, E.C. Oh, T. Thorolfsson, S. Melamed, S. Luniya, T. Doxsee, S. Berkeley, B. Shani and K. Obermiller, "Design and CAD for 3D Integrated Circuits," IEEE/ACM Design Automation Conference, pp. 668-673, June 2008
[46] C.-H. Lu, H.-M. Chen, C.-N. Liu and W.-Y. Shih, "An I/O Planning Method for Three-Dimensional Integrated Circuits," Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 198-202, October 2007
[47] J. Minz and S. Lim, "Block-level 3-d Global Routing with an Application to 3-d Packaging," IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 25, no. 10, pp. 2248-2257, October 2006
[48] J.-M. Minz, E. Wong, M. Pathak and S.-K. Lim, "Placement and Routing for 3-d System-on-package Designs," IEEE Transactions on Components and Packaging Technology, vol. 29, no. 3, pp. 644-657, September 2006
[49] R. Hentschke, G. Flach, F. Pinto and R. Reis, "An Algorithm for I/O Partitioning Targeting 3d Circuits and Its Impact on 3d-vias," IEEE International Conference on Very Large Scale Integration, pp. 128-133, 2006
[50] G. Karypis, R. Aggarwal, V. Kumar and S. Shekhar, "Multilevel Hypergraph Partitioning: Application in Vlsi Domain," IEEE/ACM Design Automation Conference, pp. 526-529, June 1997
[51] C. Fiduccia and R. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions," IEEE/ACM Design Automation Conference, pp. 175-181, June 1982
[52] S. Souri, K. Banerjee, A. Mehrotra and K. Saraswat, "Multiple Si Layer Ics: Motivation, Performance Analysis, and Design Implications," IEEE/ACM Design Automation Conference, pp. 213-220, June 2000
[53] K. Takahashi and M. Sekiguchi, "Through Silicon Via and 3-d Wafer/chip Stacking Technology," IEEE Symposium on VLSI Circuits Digest of Technical, pp. 89-92, 2006
[54] P. D. Franzon, W. Davis, M. Steer, H. Hao, S. Lipa, S. Luniya, C. Mineo, J. Oh, A. Sule and T. Thorolfsson, "Design for 3d Integration and Applications," International Symposium on Signals, Systems and Electronics, pp. 263-266, August 2007
[55] B. Kernighan and S. Lin, "An Efficient Heuristic Procedure to Partition Graphs," Bell System Technical Journal, vol. 49, pp. 291-307, February 1970
[56] S. Dutt and W. Deng, "Vlsi Circuit Partitioning by Cluster-removal Using Iterative Improvement Techniques," IEEE International Conference on Computer Design, pp. 194-200, October 1996
[57] J. Cong, J. Wei and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," IEEE International Conference on Computer Design, pp. 306-313, November 2004.
[58] J. Cong and Y. Zhang, "Thermal-Aware Physical Design Flow for 3-D ICs," IEEE International VLSI Multilevel Interconnection Conference, pp. 73-80, September 2006.
[59] E. Wong and S.-K. Lim, "3D Floorplanning with Thermal Vias," IEEE/ACM Conference of Design, Automation, and Test in Europe, pp. 878-883, April 2006
[60] Advanced Semiconductor Engineering Global. http://www.aseglobal.com