在系統晶片中，訊號同步電路扮演越來越重要的角色，鎖相迴路(Phase-Locked Loop, PLL)和延遲鎖定迴路(Delay-Locked Loop, DLL)被廣泛地運用在晶片設計裡，但是，此兩種電路在使用上需要考慮到幾個問題，第一，由於上述兩種電路屬於閉迴路系統，產生頻寬方面的問題，需要考慮電路穩定性的問題。第二，電路需要花數十到數百個時脈週期才能完成相位鎖定，在鎖定過程中需要較大的功率消耗，於是，同步複製延遲電路被設計出來，藉此改善上述的缺點。
傳統的同步複製延遲電路有三個主要的缺點，首先，電路的相位誤差會受到輸出負載改變的影響而加大。其次，輸入訊號的責任週期受到限制。最後，則是因為單位元件延遲時間太大導致電路的解析度不足。受到上述的缺點影響，導致傳統的同步延遲電路僅能應用在記憶體模組。
本論文提出一高精準度且快速鎖定之任意責任週期之時脈同步電路，不僅擁有同步複製延遲電路的優點:快速鎖定與低功率消耗，並且輸入與輸出訊號間之相位誤差≦29 ps，輸入訊號的責任可以任意調變(25%~75%)，此外，相位誤差不會因為輸出負載的改變而增加。並以TSMC 0.13μm CMOS製程實現晶片，供應電壓為1.2V，操作在最高頻率600MHz時的功率消耗為2.4mW。核心電路的面積(不含I/O PAD)為0.039mm2 ，輸出訊號之最大抖動量(peak-to-peak jitter)為25.2 ps。在論文的後半段會有量測結果，以證明提出的新電路確實改善了上述的缺點。

Clock synchronization plays a important role in designing VLSI circuit. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems in order to suppress the clock skew. However, these circuits have to consider some problems in using. First, PLL and DLL have issues of bandwidth because they are both closed loop systems. For this reason, they need to consider the stability of circuits. Second, they consume a lot of power in the process of locking. Consequently, the synchronous mirror delay circuit (SMD) was developed to improve the drawbacks.
However, there are some drawbacks in conventional SMD. First, the phase error will increase because of the output loading. Next, the duty cycle of input signal is limited. Finally, the poor resolution is due to the delay cell. These shortcomings will limit the application of the SMD.
A high precision fast locking arbitrary duty cycle clock synchronization circuit is proposed in the thesis, which not only keeps the advantage of SMD but the phase error between the input signal and output signal is less than 29 ps (simulated). And the tuning range of input signal’s duty cycle is 25% ~75%. Furthermore, the static phase error will not increase as the output loading changes. The test chip is fabricated in a 0.13-μm CMOS process and the supply voltage is 1.2V. It consumes 2.4mW when the operating frequency is 600MHz. The active area (without I/O PAD) is 0.039 mm2 , and the peak-to-peak jitter is 25.2 ps. There will be experimental results in latter half component of the thesis, which confirms the proposed circuit has improved certainly the drawbacks of SMD.

[1] Takanori Saeki, Yuji Nakaoka, Mamoru Fujita et al, “A 2.5-ns Clock Access 250-MHz 256-Mb SDRAM with A Synchronous Mirror Delay,” IEEE International Solid-State Circuits Conference Dig. Tech. Paper, pp. 374-375, Feb. 1996.
[2] Takanori Saeki, Yuji Nakaoka, Mamoru Fujita et al, “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,” IEEE J. Solid-State Circuits, vol. 31, no 11, pp. 1656-1668, Nov. 1996.
[3] Takanori Saeki, Hideyuki Nakamura, and Junzoh Shimizu “A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based on An Interleaved Synchronous Mirror Delay Scheme,” Symposium on VLSI Circuits, Dig. Tech. Paper, pp. 109-110, Jun. 1997.
[4] Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, and Hisamitsu Suzuki “The direct skew detect synchronous mirror delay (Direct SMD) for ASICs,” Custom Integrated Circuits Conference, pp. 511-514, May 1998.
[5] Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, and Hisamitsu Suzuki “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits,” IEEE J. Solid-State Circuits, vol. 34, no 3, pp. 372-379, Mar. 1999.
[6] Kihyuk Sung, Byung-Do Yang, and Lee-Sup Kim “Low Power Clock Generator Based on An Area-reduced Interleaved Synchronous Mirror Delay Scheme,” IEEE International Symposium on Circuits and Systems, vol. 3, pp. 671-674, May 2002.
[7] Kihyuk Sung, Byung-Do Yang, and Lee-Sup Kim “Low Power Clock Generator Based on Area-reduced Interleaved Synchronous Mirror Delay,” Electronics Letters, vol. 38, no.9, pp. 399-400, Apr. 2002
[8] Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, and Wonchan Kim “An Analog Synchronous Mirror Delay for High-speed DRAM Application,” IEEE J. Solid-State Circuits, vol. 34, no 4, pp. 484-493, Apr. 1999.
[9] Daeyun Shim, Yeon-Jae Jung, Seung-Wook Lee, and Wonchan Kim “Fast Locking Clock Generator Using Analog Synchronous Mirror Delay Technique with Feedback Control,” International Conference on Solid-State and Integrated-Circuits Technology, vol. 2, pp. 1125-1127, Oct. 2001.
[10] Seong-Jin Jang, Young-Hyun Jun, Jae-Goo Lee, and Bai-Sun Kon “ASMD With Duty Cycle Correction Scheme for High-Speed DRAM,” Electronics Letters, vol. 37, no.16, pp. 1004-1006, Aug. 2001.
[11] Sei Hyung Jang “A New Synchronous Mirror Delay With An Auto-Skew-Generation circuit,” IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 397-400, May 2003.
[12] Tae-Sung Kim, Sung-Ho Wang, and Beomsup Kim “A Low Jitter, Fast Locking Delay Locked Loop Using Measure And Control Scheme,” Mixed-Signal Design, SSMSD, Southwest Symposium on, pp. 45-50, Feb. 2001.
[13] Jeong-Seok Chae, Daejeong Kim, and Dong Myeong Kim “Wide Range Single-Way-Pumping Synchronous Mirror Delay,” Electronics Letters, vol. 36, no.11, pp. 939-940, May 2000.
[14] Kihyuk Sung and Lee-Sup Kim “A High-resolution Synchronous Mirror Delay Using Successive Approximation Register,” IEEE J. Solid-State Circuits, vol. 39, no 11, pp. 1997-2004, Nov. 2004.
[15] Yong Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam Seog Kim, Uk Rae Cho, and Hyun Guen Byun “Synchronous Mirror Delay For Multiphase Locking,” IEEE J. Solid-State Circuits, vol. 39, no 1, pp. 150-156, Jan. 2004.
[16] Chih-Hao Sun and Shen-Iuan Liu “A Mixed-Mode Synchronous Mirror Delay Insensitive To Supply And Load Variations,” Journal Of Analog Integrated Circuits And Signal Processings, vol. 39, pp. 75-80, Apr. 2004.
[17] Yi-Ming Wang and Jinn-Shyan Wang “A Low-power Half-Delay-Line Fast Skew-Compensation Circuit,” IEEE J. Solid-State Circuits, vol. 39, no 6, pp. 906-918, Jun. 2004.
[18] Kihyuk Sung and Lee-Sup Kim “A High-Resolution Synchronous Mirror Delay Using Successive Approximation Register,” IEEE J. Solid-State Circuits, vol. 39, no 11, pp. 1997-2004, Nov. 2004.
[19] Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo and Chia-Wei Su “A Phase-Detect Synchronous Mirror Delay For Skew-Compensation Circuit,” IEEE International Symposium on Circuits and Systems, vol.2, pp. 1070-1073, May 2005.
[20] Kuo-Hsing Cheng, Chen-Lung Wu, Chia-Wei Su and Yu-Lung Lo “A Phase-Locked Pulse Width Control Loop With Programmable Duty Cycle,” IEEE ASIA-PACIFIC Conference on ASIC, pp. 84-87, Aug. 2004.
[21] Hung, Cheng-Liang; Wu, Chen-Lung and Cheng, Kuo-Hsing “Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design,” IEEE Asian Solid-State Circuit Conference, pp. 283-286, Nov. 2006.
[22] Nakaya Hiroaki, Sasaki Yasuhiko, Kato Naoki, Arakawa Fumio and Shimizu Toru “An Alternative Cyclic Synchronous Mirror Delay for Versatility in Highly Integrated SoC,” IEEE Asian Solid-State Circuit Conference, pp. 279-282, NOV. 2006.
[23] Hong, Kai-Wei, Lee Chien-Hsien, Cheng Kuo-Hsing, Wu Chen-Lung and Yang Wei-Bin “A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay,” IEEE International Conference on Electronics, Circuits and Systems, pp. 569-572, Dec. 2006.
[24] Tsung-Chu Huang, Gau-Bin Chang and Ling Li “Congruence Synchronous Mirror Delay,” IEEE International Symposium on Circuits and Systems, pp.2184-2187, May 2007.
[25] Zeng Xianjun, Ji Rong, Huang Shizhen, Chen Liang, Luo Gang and Zhang Junfeng “A Novel Clock Duty-Cycle Corrector of DSP Systems,” Congress on Image and Signal Processing, vol.2, pp.561-564, May 2008.