| 研究生: |
林慶和 Ching-Ho Lin |
|---|---|
| 論文名稱: |
適用於類比電路區塊之解析式行為模型產生器及數位化建模技術 Analytical Behavioral Model Generator for Analog Circuit Blocks with Digitalized Modeling Technique |
| 指導教授: |
劉建男
Chien-Nan Jimmy Liu |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2016 |
| 畢業學年度: | 105 |
| 語文別: | 中文 |
| 論文頁數: | 77 |
| 中文關鍵詞: | 類比電路 、行為模型產生器 、建模技術 |
| 外文關鍵詞: | analog circuit, behavioral model generator, modeling |
| 相關次數: | 點閱:10 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
建立每個電路的行為模型是一種驗證混合信號系統層級的有效方法,如果能發展一個自動行為產生器,可以從電路規格或連線關係自動產生此模塊所需的行為模型,就能有效地協助設計者減少額外工作時間。因此,本論文中提出一個自動化的方法來建立所需的行為模型,以加快混合信號系統的驗證。
對於一些常用的電路模塊,我們採用專用行為模型產生器,直接從給定的電路規格產生相對應的行為模型。對於其他的電路塊則採用分而治之的辦法,從給定的電路中萃取所需的行為模型。在本論文提出的方法中,我們並不會直接模擬電路的輸入和輸出之間的關係,而是將大電路模塊劃分成幾個小的模塊,可以大大的降低不同的電路的模型建設時間,卻又不失一般性。如實驗結果所示,所提出的自動模型產生器確實可以自動生成對應的行為模型,並具備相當良好的精確度。
Building the behavioral model for each circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available to generate the required behavioral model from the given circuit specifications or netlist, it is useful for designers to reduce the extra efforts. In this paper, a automation methodologies are proposed to build the behavioral models for speeding up mixed-signal system verification.
For some popular circuit blocks, dedicated behavioral model generators are developed to obtain the corresponding models directly from the given specifications. For generic circuit blocks, a divide and conquer approach is proposed to extract the required behavioral models from the given circuit netlist. Instead of modeling the relationship between circuit inputs and outputs directly, dividing the circuit into several small building blocks can greatly reduce the model construction efforts without losing the generality for different circuits. As shown in the experimental results, the proposed model generation environment does generate the corresponding behavioral models automatically with good accuracy.
[1] http://www.cadence.com/eu/Documents/MicrosoftPowerPoint ToT2013openend.pdf
[2] https://verificationacademy.com/verification-horizons/october-2012-volume-8-issue-3/improving-analog-mixed-signal-verification-productivity
[3] A. Demir and J. Roychowdhury, “A Reliable and Efficient Procedure for Oscillator PPV Computation with Phase Noise Macromodeling Applications,” IEEE Trans. on Computer-Aided Design, pp. 188-197, Feb. 2003.
[4] G. Richard, “Analog/Mixed-Signal Behavioral Modeling – When to Use What”, Cadence Design Communities, February 2011.
[5] C.-C. Kuo, Y.-C. Wang, and C.-N. J. Liu, “An Efficient Bottom-Up Extraction Approach to Build Accurate PLL Behavioral Models for SOC Designs,” in Proc. Great Lakes Symp. on VLSI, pp. 286-290, Apr. 2005.
[6] A. Mounir, A. Mostafa, and M. Fikry, “Automatic Behavioural Model Calibration for Efficient PLL System Verification,” in Proc. Design, Automation and Test in Europe Conf., pp. 280-285, 2003.
[7] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. on Circuits and Systems I, pp. 352-364, Mar 2003.
[8] W.-H. Cheng, C.-C. Kuo, P.-J. Chen, Y.-M. Wang, and C.-N. J. Liu, “An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor Sigma-Delta Modulator,” in Proc. Int’l Workshop on Behavioral Modeling and Simulation, pp. 17-21, Sep. 2007.
[9] M. Rewienski, J. White, “A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices,” IEEE Trans. on Computer-Aided Design, pp. 155-170, Feb. 2003.
[10] R.A Rutenbar; G.G.E. Gielen; J Roychowdhury, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs”, Proceedings of the IEEE, pages 640-669, march 2007.
[11] P. Wambacq, F. Fernández, G. Gielen, W. Sansen, and A. Rodríguez-Vázquez, “Efficient symbolic computation of approximated small-signal characteristics” IEEE Journal. Solid-State Circuits, vol. 30, pages. 327–330, Mar 1995.
[12] C.-J.Richer. ; Shi., “Canonical symbolic analysis of large analog circuits with determinant decision diagrams”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages. 1-18, January 2000
[13] L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pages. 352–366, April 1990.
[14] J.-R. Li and J. White, “Efficient model reduction of interconnect via approximate system gramians”, IEEE Transacitons on Computer-Aided Design of Integrated Circuit and Systems , pages. 380–383, November 1999.
[15] K. Gallivan, “Asymptotic waveform evaluation via a Lanczos method”, Pergamon, pages 75-80, April 1944
[16] F. Mourad, T-C. Esteban, C-L. Rafael. et.al, “Analog/RF and Mixed-Signal Circuit Systematic Design”, Rafael, 2013, ISBN 978-3-642-36329-0
[17] M. Rewienski and J. White, “A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices”, IEEE Transacitons on Computer-Aided Design of Integrated Circuit and Systems, Nov 2001.
[18] http://www.analog.com/static/imported-files/tech_docs/dsp_book_Ch15.pdf
[19] 陳建宇, “基於迴歸分析之類比電路行為模型自動產生器”, 中央大學碩士論文, July 2015
[20] M. Eick, “Structure and signal path analysis for analog and digital circuits,”Ph.D. Dissertation, Dept. Electr. Eng. Inf. Technol., Technische Universitt München, München, Germany, 2013
[21] 樓禹慷,“自動辨識混合訊號電路中數位區塊之方法”,中央大學碩士論文,July 2016
[22] 王綉文, “適用於混合訊號設計的自動化電路區塊降為模型產生器”, 中央大學碩士論文, July 2014
[23] T. Massier, “The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis”, IEEE Computer-Aid Design of Integrated Circuit and Systems, December 2008
[24] C.Wenger, “Method of Modeling Analog Circuits in Verilog for Mixed-signal Design Simulations,” IEEE ECCTD 2013 European Conference on
[25] Yu-Ching Liao et.al, “LASER: layout-aware analog synthesis environment on laker”, Great lakes symposium on VLSI (GLSVLSI), May 2013.